[llvm-commits] [llvm] r134286 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/atomic-or.ll

[Eric Christopher]

Author: echristo
Date: Fri Jul  1 18:04:38 2011
New Revision: 134286

URL: http://llvm.org/viewvc/llvm-project?rev=134286&view=rev
Log:
TargetConstant immediates won't be placed into registers so tighten
up the valid constant check earlier.

rdar://9692967

Modified:
    llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/X86/atomic-or.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=134286&r1=134285&r2=134286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jul  1 18:04:38 2011
@@ -23,6 +23,7 @@
 #include "llvm/Intrinsics.h"
 #include "llvm/Support/CFG.h"
 #include "llvm/Type.h"
+#include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1351,7 +1352,7 @@
 
   bool isInc = false, isDec = false, isSub = false, isCN = false;
   ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
-  if (CN) {
+  if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) {
     isCN = true;
     int64_t CNVal = CN->getSExtValue();
     if (CNVal == 1)
@@ -1371,6 +1372,7 @@
     Val = Val.getOperand(1);
   }
 
+  DebugLoc dl = Node->getDebugLoc();
   unsigned Opc = 0;
   switch (NVT.getSimpleVT().SimpleTy) {
   default: return 0;
@@ -1462,7 +1464,6 @@
     break;
   }
 
-  DebugLoc dl = Node->getDebugLoc();
   SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
                                                  dl, NVT), 0);
   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
@@ -1579,7 +1580,7 @@
   
   bool isCN = false;
   ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
-  if (CN) {
+  if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) {
     isCN = true;
     Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
   }

Modified: llvm/trunk/test/CodeGen/X86/atomic-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-or.ll?rev=134286&r1=134285&r2=134286&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic-or.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic-or.ll Fri Jul  1 18:04:38 2011
@@ -2,17 +2,35 @@
 
 ; rdar://9692967
 
-define void @do_the_sync(i64* %p, i32 %b) nounwind {
+define void @t1(i64* %p, i32 %b) nounwind {
 entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+; CHECK: t1:
+; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
-; CHECK-NEXT: orq     $2147483648
+; CHECK-NEXT: orq %rax, (%rdi)
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void
 }
+
+define void @t2(i64* %p, i32 %b) nounwind {
+entry:
+  %p.addr = alloca i64*, align 8
+  store i64* %p, i64** %p.addr, align 8
+  %tmp = load i64** %p.addr, align 8
+  call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+; CHECK: t2:
+; CHECK-NOT: movl
+; CHECK: lock
+; CHECK-NEXT: orq $2147483644, (%rdi)
+  %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644)
+  call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
+  ret void
+}
+
 declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind
 declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind