[llvm-commits] [llvm] r134204 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMFrameLowering.cpp ARMInstrThumb.td Thumb1FrameLowering.cpp Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Thumb2SizeReductio
Eli Friedman
eli.friedman at gmail.com
Thu Jun 30 17:16:51 PDT 2011
On Thu, Jun 30, 2011 at 4:38 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Thu Jun 30 18:38:17 2011
> New Revision: 134204
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134204&view=rev
> Log:
> Refact ARM Thumb1 tMOVr instruction family.
>
> Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
> into tMOVr. There's no need to keep them separate. Giving the tMOVr
> instruction the proper GPR register class for its operands is sufficient
> to give the register allocator enough information to do the right thing
> directly.
Does this account for the fact that "mov r1, r2" is illegal on pre-v6
Thumb1 implementations?
-Eli
> Modified:
> llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
> llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 18:38:17 2011
> @@ -1010,8 +1010,6 @@
> MI->dump();
> assert(0 && "Unsupported opcode for unwinding information");
> case ARM::MOVr:
> - case ARM::tMOVgpr2gpr:
> - case ARM::tMOVgpr2tgpr:
> Offset = 0;
> break;
> case ARM::ADDri:
> @@ -1456,7 +1454,7 @@
> case ARM::t2BR_JT: {
> // Lower and emit the instruction itself, then the jump table following it.
> MCInst TmpInst;
> - TmpInst.setOpcode(ARM::tMOVgpr2gpr);
> + TmpInst.setOpcode(ARM::tMOVr);
> TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
> // Add predicate operands.
> @@ -1505,7 +1503,7 @@
> // mov pc, target
> MCInst TmpInst;
> unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
> - ARM::MOVr : ARM::tMOVgpr2gpr;
> + ARM::MOVr : ARM::tMOVr;
> TmpInst.setOpcode(Opc);
> TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
> @@ -1518,7 +1516,7 @@
> OutStreamer.EmitInstruction(TmpInst);
>
> // Make sure the Thumb jump table is 4-byte aligned.
> - if (Opc == ARM::tMOVgpr2gpr)
> + if (Opc == ARM::tMOVr)
> EmitAlignment(2);
>
> // Output the data for the jump table itself
> @@ -1610,7 +1608,7 @@
> MCSymbol *Label = GetARMSJLJEHLabel();
> {
> MCInst TmpInst;
> - TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
> + TmpInst.setOpcode(ARM::tMOVr);
> TmpInst.addOperand(MCOperand::CreateReg(ValReg));
> TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> // Predicate.
> @@ -1829,7 +1827,7 @@
> }
> {
> MCInst TmpInst;
> - TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
> + TmpInst.setOpcode(ARM::tMOVr);
> TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
> TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> // Predicate.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jun 30 18:38:17 2011
> @@ -268,13 +268,13 @@
> // bic r4, r4, MaxAlign
> // mov sp, r4
> // FIXME: It will be better just to find spare register here.
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
> .addReg(ARM::SP, RegState::Kill));
> AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
> TII.get(ARM::t2BICri), ARM::R4)
> .addReg(ARM::R4, RegState::Kill)
> .addImm(MaxAlign-1)));
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
> .addReg(ARM::R4, RegState::Kill));
> }
>
> @@ -293,7 +293,7 @@
> .addReg(ARM::SP)
> .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
> else
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> RegInfo->getBaseRegister())
> .addReg(ARM::SP));
> }
> @@ -364,7 +364,7 @@
> "No scratch register to restore SP from FP!");
> emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
> ARMCC::AL, 0, TII);
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ARM::SP)
> .addReg(ARM::R4));
> }
> @@ -374,7 +374,7 @@
> BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
> .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
> else
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ARM::SP)
> .addReg(FramePtr));
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 18:38:17 2011
> @@ -1054,15 +1054,15 @@
> // TODO: A7-73: MOV(2) - mov setting flag.
>
> let neverHasSideEffects = 1 in {
> -def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
> +def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> Size2Bytes, IIC_iMOVr,
> "mov", "\t$Rd, $Rm", "", []>,
> - T1Special<0b1000> {
> + T1Special<{1,0,?,?}> {
> // A8.6.97
> bits<4> Rd;
> bits<4> Rm;
> - // Bits {7-6} are encoded by the T1Special value.
> - let Inst{5-3} = Rm{2-0};
> + let Inst{7} = Rd{3};
> + let Inst{6-3} = Rm;
> let Inst{2-0} = Rd{2-0};
> }
> let Defs = [CPSR] in
> @@ -1075,40 +1075,6 @@
> let Inst{5-3} = Rm;
> let Inst{2-0} = Rd;
> }
> -
> -// FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
> -// They all map to the same instruction (MOV encoding T1).
> -def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - T1Special<{1,0,0,?}> {
> - // A8.6.97
> - bits<4> Rd;
> - bits<4> Rm;
> - // Bit {7} is encoded by the T1Special value.
> - let Inst{6-3} = Rm;
> - let Inst{2-0} = Rd{2-0};
> -}
> -def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
> - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - T1Special<{1,0,?,0}> {
> - // A8.6.97
> - bits<4> Rd;
> - bits<4> Rm;
> - // Bit {6} is encoded by the T1Special value.
> - let Inst{7} = Rd{3};
> - let Inst{5-3} = Rm{2-0};
> - let Inst{2-0} = Rd{2-0};
> -}
> -def tMOVgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - T1Special<{1,0,?,?}> {
> - // A8.6.97
> - bits<4> Rd;
> - bits<4> Rm;
> - let Inst{7} = Rd{3};
> - let Inst{6-3} = Rm;
> - let Inst{2-0} = Rd{2-0};
> -}
> } // neverHasSideEffects
>
> // Multiply register
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jun 30 18:38:17 2011
> @@ -160,7 +160,7 @@
> // will be allocated after this, so we can still use the base pointer
> // to reference locals.
> if (RegInfo->hasBasePointer(MF))
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
> .addReg(ARM::SP));
>
> // If the frame has variable sized objects then the epilogue must restore
> @@ -240,11 +240,11 @@
> "No scratch register to restore SP from FP!");
> emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
> TII, *RegInfo);
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ARM::SP)
> .addReg(ARM::R4));
> } else
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ARM::SP)
> .addReg(FramePtr));
> } else {
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -36,17 +36,7 @@
> MachineBasicBlock::iterator I, DebugLoc DL,
> unsigned DestReg, unsigned SrcReg,
> bool KillSrc) const {
> - bool tDest = ARM::tGPRRegClass.contains(DestReg);
> - bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
> - unsigned Opc = ARM::tMOVgpr2gpr;
> - if (tDest && tSrc)
> - Opc = ARM::tMOVr;
> - else if (tSrc)
> - Opc = ARM::tMOVtgpr2gpr;
> - else if (tDest)
> - Opc = ARM::tMOVgpr2tgpr;
> -
> - AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
> + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
> .addReg(SrcReg, getKillRegState(KillSrc)));
> assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
> "Thumb1 can only copy GPR registers");
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -417,7 +417,7 @@
> unsigned PredReg;
> if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
> // Turn it into a move.
> - MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
> + MI.setDesc(TII.get(ARM::tMOVr));
> MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
> // Remove offset and add predicate operands.
> MI.RemoveOperand(FrameRegIdx+1);
> @@ -564,7 +564,7 @@
> // the function, the offset will be negative. Use R12 instead since that's
> // a call clobbered register that we know won't be used in Thumb1 mode.
> DebugLoc DL;
> - AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
> + AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
> .addReg(ARM::R12, RegState::Define)
> .addReg(Reg, RegState::Kill));
>
> @@ -589,7 +589,7 @@
> }
> }
> // Restore the register from R12
> - AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
> + AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
> addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
>
> return true;
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Thu Jun 30 18:38:17 2011
> @@ -98,9 +98,6 @@
> case ARM::MOVr:
> case ARM::MOVr_TC:
> case ARM::tMOVr:
> - case ARM::tMOVgpr2tgpr:
> - case ARM::tMOVtgpr2gpr:
> - case ARM::tMOVgpr2gpr:
> case ARM::t2MOVr:
> return true;
> }
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -112,17 +112,7 @@
> if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
> return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
>
> - bool tDest = ARM::tGPRRegClass.contains(DestReg);
> - bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
> - unsigned Opc = ARM::tMOVgpr2gpr;
> - if (tDest && tSrc)
> - Opc = ARM::tMOVr;
> - else if (tSrc)
> - Opc = ARM::tMOVtgpr2gpr;
> - else if (tDest)
> - Opc = ARM::tMOVgpr2tgpr;
> -
> - AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
> + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
> .addReg(SrcReg, getKillRegState(KillSrc)));
> }
>
> @@ -231,7 +221,7 @@
> unsigned Opc = 0;
> if (DestReg == ARM::SP && BaseReg != ARM::SP) {
> // mov sp, rn. Note t2MOVr cannot be used.
> - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
> + AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
> .addReg(BaseReg).setMIFlags(MIFlags));
> BaseReg = ARM::SP;
> continue;
> @@ -409,7 +399,7 @@
> unsigned PredReg;
> if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
> // Turn it into a move.
> - MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
> + MI.setDesc(TII.get(ARM::tMOVr));
> MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
> // Remove offset and remaining explicit predicate operands.
> do MI.RemoveOperand(FrameRegIdx+1);
> @@ -575,8 +565,7 @@
> Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
> MachineInstr *UseMI,
> const TargetRegisterInfo &TRI) const {
> - if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
> - SrcMI->getOperand(1).isKill())
> + if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
> return;
>
> unsigned PredReg = 0;
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Jun 30 18:38:17 2011
> @@ -82,7 +82,7 @@
> { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 },
> { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 },
> // FIXME: Do we need the 16-bit 'S' variant?
> - { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0,0 },
> + { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0 },
> { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0,0 },
> { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0,0 },
> { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 },
>
>
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