[llvm-commits] [PATCH]: ppc32 va_arg() implementation

Roman Divacky rdivacky at freebsd.org
Mon Jun 27 10:00:07 PDT 2011 

Now with a test case, the testcase tests i32 (uses gpr_index).
f32 (uses fpr_index) and i64 (uses aligned gpr_index).

OK to commit?

On Tue, Jun 14, 2011 at 09:47:27PM +0200, Roman Divacky wrote:
> Hi,
> 
> the attached patch implements va_arg() lowering on ppc32.
> Ints (8, 16, 32 and also 64 bits that need special treatment) work,
> floats don't work (neither with gcc - we should warn when someone tries
> to use them on ppc32 probably), doubles do work. Both passing via
> register_save_area and overflow_area works.
> 
> I tried with stuff like
> 
>   foo(1, 7, 0xf00ba4cafeLL, 3.0f, 2, 4, 5, (6LL << 32) + 5LL, 7, 8, 9, 10, 11,  0);
>   bar(1, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 0.0);
> 
> I'll have some test cases soon too.
> 
> This only works at -O0 because of unrelated bugs in the PowerPC backend.
> 
> Comments?
> 
> roman


> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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; RUN: llc -O0 < %s | FileCheck %s
;ModuleID = 'test.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
target triple = "powerpc-unknown-freebsd9.0"

%struct.__va_list_tag = type { i8, i8, i16, i8*, i8* }

@var1 = common global i64 0, align 8
@var2 = common global double 0.0, align 8
@var3 = common global i32 0, align 4

define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
 entry:
  %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
; CHECK:      lbz 4, 0(3)
; CHECK-NEXT: lwz 5, 4(3)
; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
; CHECK-NEXT: cmplwi 0, 6, 0
; CHECK-NEXT: addi 6, 4, 1
; CHECK-NEXT: stw 3, -4(1)
; CHECK-NEXT: stw 6, -8(1)
; CHECK-NEXT: stw 4, -12(1)
; CHECK-NEXT: stw 5, -16(1)
; CHECK-NEXT: bne 0, .LBB0_2
; CHECK-NEXT: # BB#1:                                 # %entry
; CHECK-NEXT: lwz 3, -12(1)
; CHECK-NEXT: stw 3, -8(1)
; CHECK-NEXT: .LBB0_2:                                # %entry
; CHECK-NEXT: lwz 3, -8(1)
; CHECK-NEXT: lwz 4, -4(1)
; CHECK-NEXT: lwz 5, 8(4)
; CHECK-NEXT: slwi 6, 3, 2
; CHECK-NEXT: addi 7, 3, 2
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: lwz 3, -16(1)
; CHECK-NEXT: addi 8, 3, 4
; CHECK-NEXT: add 5, 5, 6
; CHECK-NEXT: mfcr 0                          # cr0
; CHECK-NEXT: stw 0, -20(1)
; CHECK-NEXT: stw 5, -24(1)
; CHECK-NEXT: stw 3, -28(1)
; CHECK-NEXT: stw 7, -32(1)
; CHECK-NEXT: stw 8, -36(1)
; CHECK-NEXT: blt 0, .LBB0_4
; CHECK-NEXT: # BB#3:                                 # %entry
; CHECK-NEXT: lwz 3, -36(1)
; CHECK-NEXT: stw 3, -28(1)
; CHECK-NEXT: .LBB0_4:                                # %entry
; CHECK-NEXT: lwz 3, -28(1)
; CHECK-NEXT: lwz 4, -32(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 0(5)
; CHECK-NEXT: lwz 4, -24(1)
; CHECK-NEXT: lwz 0, -20(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 3, -40(1)
; CHECK-NEXT: stw 4, -44(1)
; CHECK-NEXT: blt 0, .LBB0_6
; CHECK-NEXT: # BB#5:                                 # %entry
; CHECK-NEXT: lwz 3, -16(1)
; CHECK-NEXT: stw 3, -44(1)
; CHECK-NEXT: .LBB0_6:                                # %entry
; CHECK-NEXT: lwz 3, -44(1)
; CHECK-NEXT: lwz 4, -40(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
  store i64 %x, i64* @var1, align 8
; CHECK-NEXT: lis 4, var1 at ha
; CHECK-NEXT: lwz 6, 4(3)
; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: la 7, var1 at l(4)
; CHECK-NEXT: stw 3, var1 at l(4)
; CHECK-NEXT: stw 6, 4(7)
  %y = va_arg %struct.__va_list_tag* %ap, double; From f1
; CHECK-NEXT: lbz 3, 1(5)
; CHECK-NEXT: lwz 4, 4(5)
; CHECK-NEXT: lwz 6, 8(5)
; CHECK-NEXT: slwi 7, 3, 3
; CHECK-NEXT: add 6, 6, 7
; CHECK-NEXT: addi 7, 3, 1
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: addi 3, 4, 8
; CHECK-NEXT: addi 6, 6, 32
; CHECK-NEXT: mr 8, 4
; CHECK-NEXT: mfcr 0                          # cr0
; CHECK-NEXT: stw 0, -48(1)
; CHECK-NEXT: stw 4, -52(1)
; CHECK-NEXT: stw 6, -56(1)
; CHECK-NEXT: stw 7, -60(1)
; CHECK-NEXT: stw 3, -64(1)
; CHECK-NEXT: stw 8, -68(1)
; CHECK-NEXT: blt 0, .LBB0_8
; CHECK-NEXT: # BB#7:                                 # %entry
; CHECK-NEXT: lwz 3, -64(1)
; CHECK-NEXT: stw 3, -68(1)
; CHECK-NEXT: .LBB0_8:                                # %entry
; CHECK-NEXT: lwz 3, -68(1)
; CHECK-NEXT: lwz 4, -60(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 1(5)
; CHECK-NEXT: lwz 4, -56(1)
; CHECK-NEXT: lwz 0, -48(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 4, -72(1)
; CHECK-NEXT: stw 3, -76(1)
; CHECK-NEXT: blt 0, .LBB0_10
; CHECK-NEXT: # BB#9:                                 # %entry
; CHECK-NEXT: lwz 3, -52(1)
; CHECK-NEXT: stw 3, -72(1)
; CHECK-NEXT: .LBB0_10:                               # %entry
; CHECK-NEXT: lwz 3, -72(1)
; CHECK-NEXT: lwz 4, -76(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
; CHECK-NEXT: lfd 0, 0(3)
  store double %y, double* @var2, align 8
; CHECK-NEXT: lis 3, var2 at ha
; CHECK-NEXT: stfd 0, var2 at l(3)
  %z = va_arg %struct.__va_list_tag* %ap, i32; From r7
; CHECK-NEXT: lbz 3, 0(5)
; CHECK-NEXT: lwz 4, 4(5)
; CHECK-NEXT: lwz 6, 8(5)
; CHECK-NEXT: slwi 7, 3, 2
; CHECK-NEXT: addi 8, 3, 1
; CHECK-NEXT: cmpwi 0, 3, 8
; CHECK-NEXT: addi 3, 4, 4
; CHECK-NEXT: add 6, 6, 7
; CHECK-NEXT: mr 7, 4
; CHECK-NEXT: stw 6, -80(1)
; CHECK-NEXT: stw 8, -84(1)
; CHECK-NEXT: stw 3, -88(1)
; CHECK-NEXT: stw 4, -92(1)
; CHECK-NEXT: stw 7, -96(1)
; CHECK-NEXT: mfcr 0                          # cr0
; CHECK-NEXT: stw 0, -100(1)
; CHECK-NEXT: blt 0, .LBB0_12
; CHECK-NEXT: # BB#11:                                # %entry
; CHECK-NEXT: lwz 3, -88(1)
; CHECK-NEXT: stw 3, -96(1)
; CHECK-NEXT: .LBB0_12:                               # %entry
; CHECK-NEXT: lwz 3, -96(1)
; CHECK-NEXT: lwz 4, -84(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stb 4, 0(5)
; CHECK-NEXT: lwz 4, -80(1)
; CHECK-NEXT: lwz 0, -100(1)
; CHECK-NEXT: mtcrf 128, 0
; CHECK-NEXT: stw 4, -104(1)
; CHECK-NEXT: stw 3, -108(1)
; CHECK-NEXT: blt 0, .LBB0_14
; CHECK-NEXT: # BB#13:                                # %entry
; CHECK-NEXT: lwz 3, -92(1)
; CHECK-NEXT: stw 3, -104(1)
; CHECK-NEXT: .LBB0_14:                               # %entry
; CHECK-NEXT: lwz 3, -104(1)
; CHECK-NEXT: lwz 4, -108(1)
; CHECK-NEXT: lwz 5, -4(1)
; CHECK-NEXT: stw 4, 4(5)
; CHECK-NEXT: lwz 3, 0(3)
  store i32 %z, i32* @var3, align 4
; CHECK-NEXT: lis 4, var3 at ha
; CHECK-NEXT: stw 3, var3 at l(4)
  ret void
; CHECK-NEXT: stw 5, -112(1)
; CHECK-NEXT: blr
}

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