[llvm-commits] [llvm] r133524 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/bitcast2.ll test/CodeGen/X86/vec_set-8.ll test/CodeGen/X86/vec_set-9.ll test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_shuffle-14.ll test/CodeGen/X86/vec_shuffle-17.ll test/MC/X86/x86-64.s test/MC/X86/x86_64-avx-encoding.s
Bob Wilson
bob.wilson at apple.com
Tue Jun 21 10:35:14 PDT 2011
Author: bwilson
Date: Tue Jun 21 12:35:13 2011
New Revision: 133524
URL: http://llvm.org/viewvc/llvm-project?rev=133524&view=rev
Log:
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/bitcast2.ll
llvm/trunk/test/CodeGen/X86/vec_set-8.ll
llvm/trunk/test/CodeGen/X86/vec_set-9.ll
llvm/trunk/test/CodeGen/X86/vec_set-C.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
llvm/trunk/test/MC/X86/x86-64.s
llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 21 12:35:13 2011
@@ -2850,11 +2850,11 @@
[(set VR128:$dst,
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
- "movq\t{$src, $dst|$dst, $src}",
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v2i64 (scalar_to_vector GR64:$src)))]>;
def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
- "movq\t{$src, $dst|$dst, $src}",
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
[(set FR64:$dst, (bitconvert GR64:$src))]>;
@@ -2895,7 +2895,7 @@
(iPTR 0))), addr:$dst)]>;
def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
- "movq\t{$src, $dst|$dst, $src}",
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
(iPTR 0)))]>;
def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
@@ -2903,7 +2903,7 @@
[(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
- "movq\t{$src, $dst|$dst, $src}",
+ "mov{d|q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (bitconvert FR64:$src))]>;
def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
"movq\t{$src, $dst|$dst, $src}",
@@ -2931,7 +2931,7 @@
(v4i32 (scalar_to_vector GR32:$src)))))]>,
VEX;
def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
- "movq\t{$src, $dst|$dst, $src}", // X86-64 only
+ "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
[(set VR128:$dst, (v2i64 (X86vzmovl
(v2i64 (scalar_to_vector GR64:$src)))))]>,
VEX, VEX_W;
@@ -2942,7 +2942,7 @@
[(set VR128:$dst, (v4i32 (X86vzmovl
(v4i32 (scalar_to_vector GR32:$src)))))]>;
def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
- "movq\t{$src, $dst|$dst, $src}", // X86-64 only
+ "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
[(set VR128:$dst, (v2i64 (X86vzmovl
(v2i64 (scalar_to_vector GR64:$src)))))]>;
}
@@ -2968,21 +2968,6 @@
(MOVZDI2PDIrm addr:$src)>;
}
-// We used to emit this syntax to work around a bug in the Darwin assembler,
-// so we'll continue to assemble it.
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
- (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
-
//===---------------------------------------------------------------------===//
// SSE2 - Move Quadword
//===---------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/X86/bitcast2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast2.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast2.ll Tue Jun 21 12:35:13 2011
@@ -1,31 +1,13 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | grep movd | count 2
; RUN: llc < %s -march=x86-64 | not grep rsp
define i64 @test1(double %A) {
-; CHECK: test1
-; CHECK: movq
%B = bitcast double %A to i64
ret i64 %B
}
define double @test2(i64 %A) {
-; CHECK: test2
-; CHECK: movq
%B = bitcast i64 %A to double
ret double %B
}
-define i32 @test3(float %A) {
-; CHECK: test3
-; CHECK: movd
- %B = bitcast float %A to i32
- ret i32 %B
-}
-
-define float @test4(i32 %A) {
-; CHECK: test4
-; CHECK: movd
- %B = bitcast i32 %A to float
- ret float %B
-}
-
Modified: llvm/trunk/test/CodeGen/X86/vec_set-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-8.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-8.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK-NOT: movsd
-; CHECK: movq {{%rdi|%rcx}}, %xmm0
+; CHECK: movd {{%rdi|%rcx}}, %xmm0
; CHECK-NOT: movsd
define <2 x i64> @test(i64 %i) nounwind {
Modified: llvm/trunk/test/CodeGen/X86/vec_set-9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-9.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-9.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-9.ll Tue Jun 21 12:35:13 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep movq | count 1
+; RUN: llc < %s -march=x86-64 | grep movd | count 1
; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
define <2 x i64> @test3(i64 %A) nounwind {
Modified: llvm/trunk/test/CodeGen/X86/vec_set-C.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-C.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-C.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-C.ll Tue Jun 21 12:35:13 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
define <2 x i64> @t1(i64 %x) nounwind {
%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86 -mattr=+sse2
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 4
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
define <4 x i32> @t1(i32 %a) nounwind {
Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
; CHECK-NOT: xor
-; CHECK: movq {{%rdi|%rcx}}, %xmm0
+; CHECK: movd {{%rdi|%rcx}}, %xmm0
; CHECK-NOT: xor
; PR2108
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Tue Jun 21 12:35:13 2011
@@ -1128,11 +1128,3 @@
// CHECK: strq
// CHECK: encoding: [0x48,0x0f,0x00,0xc8]
str %rax
-
-// CHECK: movq %rdi, %xmm0
-// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
- movq %rdi,%xmm0
-
-// CHECK: movq %rdi, %xmm0
-// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
- movd %rdi,%xmm0
Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Tue Jun 21 12:35:13 2011
@@ -1444,9 +1444,9 @@
// CHECK: encoding: [0xc5,0x79,0x7e,0x30]
vmovd %xmm14, (%rax)
-// CHECK: vmovd %eax, %xmm14
-// CHECK: encoding: [0xc5,0x79,0x6e,0xf0]
- vmovd %eax, %xmm14
+// CHECK: vmovd %rax, %xmm14
+// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
+ vmovd %rax, %xmm14
// CHECK: vmovq %xmm14, (%rax)
// CHECK: encoding: [0xc5,0x79,0xd6,0x30]
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