[llvm-commits] [llvm] r133063 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
Andrew Trick
atrick at apple.com
Wed Jun 15 10:56:29 PDT 2011
Self review: This test will fail in the no-Asserts build because -stress-sched is unavailable. It seems that llvm-lit always picks up the Asserts build. But is there some formal way to indicate that the test should not be run unless built with Asserts?
-Andy
On Jun 15, 2011, at 10:16 AM, Andrew Trick wrote:
> Author: atrick
> Date: Wed Jun 15 12:16:12 2011
> New Revision: 133063
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133063&view=rev
> Log:
> Added -stress-sched flag in the Asserts build.
> Added a test case for handling physreg aliases during pre-RA-sched.
>
> Added:
> llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
> Modified:
> llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
> llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=133063&r1=133062&r2=133063&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Wed Jun 15 12:16:12 2011
> @@ -497,6 +497,12 @@
> SUnit EntrySU; // Special node for the region entry.
> SUnit ExitSU; // Special node for the region exit.
>
> +#ifdef NDEBUG
> + static const bool StressSched = false;
> +#else
> + bool StressSched;
> +#endif
> +
> explicit ScheduleDAG(MachineFunction &mf);
>
> virtual ~ScheduleDAG();
>
> Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=133063&r1=133062&r2=133063&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Wed Jun 15 12:16:12 2011
> @@ -19,17 +19,27 @@
> #include "llvm/Target/TargetMachine.h"
> #include "llvm/Target/TargetInstrInfo.h"
> #include "llvm/Target/TargetRegisterInfo.h"
> +#include "llvm/Support/CommandLine.h"
> #include "llvm/Support/Debug.h"
> #include "llvm/Support/raw_ostream.h"
> #include <climits>
> using namespace llvm;
>
> +#ifndef NDEBUG
> +cl::opt<bool> StressSchedOpt(
> + "stress-sched", cl::Hidden, cl::init(false),
> + cl::desc("Stress test instruction scheduling"));
> +#endif
> +
> ScheduleDAG::ScheduleDAG(MachineFunction &mf)
> : TM(mf.getTarget()),
> TII(TM.getInstrInfo()),
> TRI(TM.getRegisterInfo()),
> MF(mf), MRI(mf.getRegInfo()),
> EntrySU(), ExitSU() {
> +#ifndef NDEBUG
> + StressSched = StressSchedOpt;
> +#endif
> }
>
> ScheduleDAG::~ScheduleDAG() {}
> @@ -307,6 +317,8 @@
> if (I->isArtificial())
> dbgs() << " *";
> dbgs() << ": Latency=" << I->getLatency();
> + if (I->isAssignedRegDep())
> + dbgs() << " Reg=" << G->TRI->getName(I->getReg());
> dbgs() << "\n";
> }
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=133063&r1=133062&r2=133063&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Jun 15 12:16:12 2011
> @@ -1369,6 +1369,21 @@
> bool isReady(SUnit* SU, unsigned CurCycle) const { return true; }
> };
>
> +#ifndef NDEBUG
> +template<class SF>
> +struct reverse_sort : public queue_sort {
> + SF &SortFunc;
> + reverse_sort(SF &sf) : SortFunc(sf) {}
> + reverse_sort(const reverse_sort &RHS) : SortFunc(RHS.SortFunc) {}
> +
> + bool operator()(SUnit* left, SUnit* right) const {
> + // reverse left/right rather than simply !SortFunc(left, right)
> + // to expose different paths in the comparison logic.
> + return SortFunc(right, left);
> + }
> +};
> +#endif // NDEBUG
> +
> /// bu_ls_rr_sort - Priority function for bottom up register pressure
> // reduction scheduler.
> struct bu_ls_rr_sort : public queue_sort {
> @@ -1569,20 +1584,33 @@
> };
>
> template<class SF>
> -class RegReductionPriorityQueue : public RegReductionPQBase {
> - static SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker) {
> - std::vector<SUnit *>::iterator Best = Q.begin();
> - for (std::vector<SUnit *>::iterator I = llvm::next(Q.begin()),
> - E = Q.end(); I != E; ++I)
> - if (Picker(*Best, *I))
> - Best = I;
> - SUnit *V = *Best;
> - if (Best != prior(Q.end()))
> - std::swap(*Best, Q.back());
> - Q.pop_back();
> - return V;
> +static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) {
> + std::vector<SUnit *>::iterator Best = Q.begin();
> + for (std::vector<SUnit *>::iterator I = llvm::next(Q.begin()),
> + E = Q.end(); I != E; ++I)
> + if (Picker(*Best, *I))
> + Best = I;
> + SUnit *V = *Best;
> + if (Best != prior(Q.end()))
> + std::swap(*Best, Q.back());
> + Q.pop_back();
> + return V;
> +}
> +
> +template<class SF>
> +SUnit *popFromQueue(std::vector<SUnit*> &Q, SF &Picker, ScheduleDAG *DAG) {
> +#ifndef NDEBUG
> + if (DAG->StressSched) {
> + reverse_sort<SF> RPicker(Picker);
> + return popFromQueueImpl(Q, RPicker);
> }
> +#endif
> + (void)DAG;
> + return popFromQueueImpl(Q, Picker);
> +}
>
> +template<class SF>
> +class RegReductionPriorityQueue : public RegReductionPQBase {
> SF Picker;
>
> public:
> @@ -1603,7 +1631,7 @@
> SUnit *pop() {
> if (Queue.empty()) return NULL;
>
> - SUnit *V = popFromQueue(Queue, Picker);
> + SUnit *V = popFromQueue(Queue, Picker, scheduleDAG);
> V->NodeQueueId = 0;
> return V;
> }
> @@ -1613,7 +1641,7 @@
> std::vector<SUnit*> DumpQueue = Queue;
> SF DumpPicker = Picker;
> while (!DumpQueue.empty()) {
> - SUnit *SU = popFromQueue(DumpQueue, DumpPicker);
> + SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG);
> if (isBottomUp())
> dbgs() << "Height " << SU->getHeight() << ": ";
> else
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=133063&r1=133062&r2=133063&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Jun 15 12:16:12 2011
> @@ -435,7 +435,7 @@
> // it requires a cross class copy (cost < 0). That means we are only
> // treating "expensive to copy" register dependency as physical register
> // dependency. This may change in the future though.
> - if (Cost >= 0)
> + if (Cost >= 0 && !StressSched)
> PhysReg = 0;
>
> // If this is a ctrl dep, latency is 1.
>
> Added: llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll?rev=133063&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll Wed Jun 15 12:16:12 2011
> @@ -0,0 +1,17 @@
> +; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
> +; Test interference between physreg aliases during preRAsched.
> +; mul wants an operand in AL, but call clobbers it.
> +
> +define i8 @f(i8 %v1, i8 %v2) nounwind {
> +entry:
> +; CHECK: callq
> +; CHECK: movb %{{.*}}, %al
> +; CHECK: mulb
> +; CHECK: mulb
> + %rval = tail call i8 @bar() nounwind
> + %m1 = mul i8 %v1, %v2
> + %m2 = mul i8 %m1, %rval
> + ret i8 %m2
> +}
> +
> +declare i8 @bar()
>
>
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