[llvm-commits] [llvm] r132317 - in /llvm/trunk: include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/XCore/ test/CodeGen/X86/ utils/TableGen/
Jim Grosbach
grosbach at apple.com
Wed Jun 1 17:44:00 PDT 2011
Rafael,
This patch appears to assume that all backends format register names as "%<name>" in their assembly, or at least can parse registers named as such. That's very much not true. The AsmStreamer shouldn't be hard-coding this sort of target specific logic.
$ cat t.s
.cfi_def_cfa %r0, 1
llvm-mc -triple armv7-apple-darwin10 t.s
.section __TEXT,__text,regular,pure_instructions
Assertion failed: (Tok.is(AsmToken::Identifier) && "Token is not an Identifier"), function TryParseRegister, file /Users/grosbaj/sources/llvm-a64/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 909.
0 llvm-mc 0x0000000100f1a275 PrintStackTrace(void*) + 53
1 llvm-mc 0x0000000100f1a83b SignalHandler(int) + 379
2 libSystem.B.dylib 0x00007fff81abb66a _sigtramp + 26
3 libSystem.B.dylib 0x00007fff5fbfe750 _sigtramp + 3725865216
4 llvm-mc 0x000000010004308b raise + 27
5 llvm-mc 0x000000010004314a abort + 26
6 llvm-mc 0x0000000100043124 __assert_rtn + 132
7 llvm-mc 0x0000000100353750 (anonymous namespace)::ARMAsmParser::TryParseRegister() + 160
8 llvm-mc 0x000000010033ca21 (anonymous namespace)::ARMAsmParser::ParseRegister(unsigned int&, llvm::SMLoc&, llvm::SMLoc&) + 33
9 llvm-mc 0x00000001008e1fb4 (anonymous namespace)::GenericAsmParser::ParseRegisterOrRegisterNumber(long long&, llvm::SMLoc) + 132
10 llvm-mc 0x00000001008e321b (anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc) + 91
11 llvm-mc 0x00000001008e31ac bool llvm::MCAsmParserExtension::HandleDirective<(anonymous namespace)::GenericAsmParser, &((anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc))>(llvm::MCAsmParserExtension*, llvm::StringRef, llvm::SMLoc) + 172
12 llvm-mc 0x00000001008d7c4c (anonymous namespace)::AsmParser::ParseStatement() + 10652
13 llvm-mc 0x00000001008d23cc (anonymous namespace)::AsmParser::Run(bool, bool) + 236
14 llvm-mc 0x000000010004ce0a AssembleInput(char const*) + 3786
15 llvm-mc 0x000000010004ac59 main + 313
16 llvm-mc 0x0000000100045994 start + 52
17 llvm-mc 0x0000000000000004 start + 4294682276
Stack dump:
0. Program arguments: /Users/grosbaj/sources/build-llvm-a64/Debug+Asserts/bin/llvm-mc -triple armv7-apple-darwin10 t.s
Illegal instruction
-Jim
On May 30, 2011, at 1:20 PM, Rafael Espindola wrote:
> Author: rafael
> Date: Mon May 30 15:20:15 2011
> New Revision: 132317
>
> URL: http://llvm.org/viewvc/llvm-project?rev=132317&view=rev
> Log:
> Use the dwarf->llvm mapping to print register names in the cfi
> directives.
>
> Fixes PR9826.
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetAsmInfo.h
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/lib/MC/MCAsmStreamer.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
> llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
> llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
> llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
> llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
> llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
> llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
> llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
> llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
> llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
> llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
> llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
> llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.h
> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
> llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
> llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
> llvm/trunk/test/CodeGen/X86/empty-functions.ll
> llvm/trunk/test/CodeGen/X86/pr9743.ll
> llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon May 30 15:20:15 2011
> @@ -95,6 +95,10 @@
> return TRI->getDwarfRegNum(RegNum, isEH);
> }
>
> + int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
> + return TRI->getLLVMRegNum(DwarfRegNum, isEH);
> + }
> +
> int getSEHRegNum(unsigned RegNum) const {
> return TRI->getSEHRegNum(RegNum);
> }
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -802,6 +802,8 @@
> /// debugging info.
> virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
>
> + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
> +
> /// getFrameRegister - This method should return the register used as a base
> /// for values allocated in the current stack frame.
> virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
>
> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon May 30 15:20:15 2011
> @@ -54,6 +54,8 @@
>
> bool needsSet(const MCExpr *Value);
>
> + void EmitRegisterName(int64_t Register);
> +
> public:
> MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
> bool isVerboseAsm, bool useLoc, bool useCFI,
> @@ -819,13 +821,25 @@
> EmitEOL();
> }
>
> +void MCAsmStreamer::EmitRegisterName(int64_t Register) {
> + if (InstPrinter) {
> + const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo();
> + unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true);
> + OS << '%' << InstPrinter->getRegName(LLVMRegister);
> + } else {
> + OS << Register;
> + }
> +}
> +
> void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
> MCStreamer::EmitCFIDefCfa(Register, Offset);
>
> if (!UseCFI)
> return;
>
> - OS << "\t.cfi_def_cfa " << Register << ", " << Offset;
> + OS << "\t.cfi_def_cfa ";
> + EmitRegisterName(Register);
> + OS << ", " << Offset;
> EmitEOL();
> }
>
> @@ -845,7 +859,8 @@
> if (!UseCFI)
> return;
>
> - OS << "\t.cfi_def_cfa_register " << Register;
> + OS << "\t.cfi_def_cfa_register ";
> + EmitRegisterName(Register);
> EmitEOL();
> }
>
> @@ -855,7 +870,9 @@
> if (!UseCFI)
> return;
>
> - OS << "\t.cfi_offset " << Register << ", " << Offset;
> + OS << "\t.cfi_offset ";
> + EmitRegisterName(Register);
> + OS << ", " << Offset;
> EmitEOL();
> }
>
> @@ -906,7 +923,8 @@
> if (!UseCFI)
> return;
>
> - OS << "\t.cfi_same_value " << Register;
> + OS << "\t.cfi_same_value ";
> + EmitRegisterName(Register);
> EmitEOL();
> }
>
> @@ -916,7 +934,9 @@
> if (!UseCFI)
> return;
>
> - OS << "\t.cfi_rel_offset " << Register << ", " << Offset;
> + OS << "\t.cfi_rel_offset ";
> + EmitRegisterName(Register);
> + OS << ", " << Offset;
> EmitEOL();
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -684,6 +684,10 @@
> return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
>
> +int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
> +}
> +
> unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
> const MachineFunction &MF) const {
> switch (Reg) {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -172,6 +172,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
>
> bool isLowRegister(unsigned Reg) const;
>
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -199,6 +199,11 @@
> return -1;
> }
>
> +int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
> + llvm_unreachable("What is the dwarf register number");
> + return -1;
> +}
> +
> #include "AlphaGenRegisterInfo.inc"
>
> std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -48,6 +48,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
>
> static std::string getPrettyName(unsigned reg);
> };
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -351,5 +351,11 @@
> return -1;
> }
>
> +int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
> + bool isEH) const {
> + llvm_unreachable("What is the dwarf register number");
> + return -1;
> +}
> +
> #include "BlackfinGenRegisterInfo.inc"
>
>
> Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -60,6 +60,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
>
> // Utility functions
> void adjustRegister(MachineBasicBlock &MBB,
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -328,6 +328,10 @@
> return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
>
> +int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
> + return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
> +}
> +
> int
> SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
> {
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon May 30 15:20:15 2011
> @@ -83,6 +83,7 @@
>
> //! Get DWARF debugging register number
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
>
> //! Convert D-form load/store to X-form load/store
> /*!
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -356,5 +356,9 @@
> return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0);
> }
>
> +int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
> +}
> +
> #include "MBlazeGenRegisterInfo.inc"
>
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -75,6 +75,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -242,4 +242,9 @@
> return 0;
> }
>
> +int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
> + llvm_unreachable("Not implemented yet!");
> + return 0;
> +}
> +
> #include "MSP430GenRegisterInfo.inc"
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Mon May 30 15:20:15 2011
> @@ -61,6 +61,7 @@
>
> //! Get DWARF debugging register number
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -278,4 +278,8 @@
> return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
>
> +int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
> +}
> +
> #include "MipsGenRegisterInfo.inc"
>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -63,6 +63,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -57,6 +57,9 @@
> virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const {
> return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
> + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const {
> + return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
> + }
> }; // struct PTXRegisterInfo
> } // namespace llvm
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon May 30 15:20:15 2011
> @@ -26,6 +26,9 @@
> return getInstructionName(Opcode);
> }
>
> +StringRef PPCInstPrinter::getRegName(unsigned RegNo) const {
> + return getRegisterName(RegNo);
> +}
>
> void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
> // Check for slwi/srwi mnemonics.
>
> Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Mon May 30 15:20:15 2011
> @@ -33,6 +33,7 @@
> return SyntaxVariant == 1;
> }
>
> + StringRef getRegName(unsigned RegNo) const;
> virtual void printInst(const MCInst *MI, raw_ostream &O);
> virtual StringRef getOpcodeName(unsigned Opcode) const;
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon May 30 15:20:15 2011
> @@ -487,6 +487,14 @@
> int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
> unsigned Reg = CSI[I].getReg();
> if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
> +
> + // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
> + // subregisters of CR2. We just need to emit a move of CR2.
> + if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
> + continue;
> + if (Reg == PPC::CR2UN)
> + Reg = PPC::CR2;
> +
> MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
> MachineLocation CSSrc(Reg);
> Moves.push_back(MachineMove(Label, CSDst, CSSrc));
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -702,4 +702,12 @@
> return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
> }
>
> +int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
> + // FIXME: Most probably dwarf numbers differs for Linux and Darwin
> + unsigned Flavour = Subtarget.isPPC64() ?
> + DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
> +
> + return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
> +}
> +
> #include "PPCGenRegisterInfo.inc"
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -68,6 +68,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -130,5 +130,9 @@
> return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
>
> +int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
> +}
> +
> #include "SparcGenRegisterInfo.inc"
>
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -52,6 +52,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -139,4 +139,10 @@
> return -1;
> }
>
> +int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + assert(0 && "What is the dwarf register number");
> + return -1;
> +}
> +
> +
> #include "SystemZGenRegisterInfo.inc"
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -54,6 +54,7 @@
> unsigned getEHHandlerRegister() const;
>
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon May 30 15:20:15 2011
> @@ -41,6 +41,10 @@
> &TM.getSubtarget<X86Subtarget>()));
> }
>
> +StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const {
> + return getRegisterName(RegNo);
> +}
> +
> void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
> // Try to print any aliases first.
> if (!printAliasInstr(MI, OS))
>
> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Mon May 30 15:20:15 2011
> @@ -26,6 +26,7 @@
> public:
> X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI);
>
> + StringRef getRegName(unsigned RegNo) const;
> virtual void printInst(const MCInst *MI, raw_ostream &OS);
> virtual StringRef getOpcodeName(unsigned Opcode) const;
>
>
> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Mon May 30 15:20:15 2011
> @@ -29,6 +29,10 @@
> #define GET_INSTRUCTION_NAME
> #include "X86GenAsmWriter1.inc"
>
> +StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const {
> + return getRegisterName(RegNo);
> +}
> +
> void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
> printInstruction(MI, OS);
>
>
> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Mon May 30 15:20:15 2011
> @@ -27,6 +27,7 @@
> X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
> : MCInstPrinter(MAI) {}
>
> + StringRef getRegName(unsigned RegNo) const;
> virtual void printInst(const MCInst *MI, raw_ostream &OS);
> virtual StringRef getOpcodeName(unsigned Opcode) const;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -73,29 +73,40 @@
> }
> }
>
> -/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
> -/// specific numbering, used in debug info and exception tables.
> -int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
> - const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
> - unsigned Flavour = DWARFFlavour::X86_64;
> -
> +static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
> if (!Subtarget->is64Bit()) {
> if (Subtarget->isTargetDarwin()) {
> if (isEH)
> - Flavour = DWARFFlavour::X86_32_DarwinEH;
> + return DWARFFlavour::X86_32_DarwinEH;
> else
> - Flavour = DWARFFlavour::X86_32_Generic;
> + return DWARFFlavour::X86_32_Generic;
> } else if (Subtarget->isTargetCygMing()) {
> // Unsupported by now, just quick fallback
> - Flavour = DWARFFlavour::X86_32_Generic;
> + return DWARFFlavour::X86_32_Generic;
> } else {
> - Flavour = DWARFFlavour::X86_32_Generic;
> + return DWARFFlavour::X86_32_Generic;
> }
> }
> + return DWARFFlavour::X86_64;
> +}
> +
> +/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
> +/// specific numbering, used in debug info and exception tables.
> +int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
> + const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
> + unsigned Flavour = getFlavour(Subtarget, isEH);
>
> return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
> }
>
> +/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
> +int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
> + unsigned Flavour = getFlavour(Subtarget, isEH);
> +
> + return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
> +}
> +
> int
> X86RegisterInfo::getSEHRegNum(unsigned i) const {
> int reg = getX86RegNum(i);
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon May 30 15:20:15 2011
> @@ -80,6 +80,7 @@
> /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
> /// (created by TableGen) for target dependencies.
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
>
> // FIXME: This should be tablegen'd like getDwarfRegNum is
> int getSEHRegNum(unsigned i) const;
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon May 30 15:20:15 2011
> @@ -315,6 +315,10 @@
> return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
> }
>
> +int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
> + return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
> +}
> +
> unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
> const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
>
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Mon May 30 15:20:15 2011
> @@ -75,6 +75,7 @@
>
> //! Get DWARF debugging register number
> int getDwarfRegNum(unsigned RegNum, bool isEH) const;
> + int getLLVMRegNum(unsigned RegNum, bool isEH) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll Mon May 30 15:20:15 2011
> @@ -1,5 +1,5 @@
> ; Check that eh_return & unwind_init were properly lowered
> -; RUN: llc < %s | grep %ebp | count 7
> +; RUN: llc < %s | grep %ebp | count 9
> ; RUN: llc < %s | grep %ecx | count 5
>
> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
>
> Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll Mon May 30 15:20:15 2011
> @@ -1,5 +1,5 @@
> ; Check that eh_return & unwind_init were properly lowered
> -; RUN: llc < %s | grep %rbp | count 5
> +; RUN: llc < %s | grep %rbp | count 7
> ; RUN: llc < %s | grep %rcx | count 3
>
> target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
>
> Modified: llvm/trunk/test/CodeGen/X86/empty-functions.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/empty-functions.ll?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/empty-functions.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/empty-functions.ll Mon May 30 15:20:15 2011
> @@ -20,10 +20,10 @@
> ; CHECK-FP-NEXT: :
> ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16
> ; CHECK-FP-NEXT: :
> -; CHECK-FP-NEXT: .cfi_offset 6, -16
> +; CHECK-FP-NEXT: .cfi_offset %rbp, -16
> ; CHECK-FP-NEXT: movq %rsp, %rbp
> ; CHECK-FP-NEXT: :
> -; CHECK-FP-NEXT: .cfi_def_cfa_register 6
> +; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp
> ; CHECK-FP-NEXT: nop
> ; CHECK-FP-NEXT: :
> ; CHECK-FP-NEXT: .cfi_endproc
>
> Modified: llvm/trunk/test/CodeGen/X86/pr9743.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9743.ll?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pr9743.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/pr9743.ll Mon May 30 15:20:15 2011
> @@ -9,9 +9,9 @@
> ; CHECK-NEXT: :
> ; CHECK-NEXT: .cfi_def_cfa_offset 16
> ; CHECK-NEXT: :
> -; CHECK-NEXT: .cfi_offset 6, -16
> +; CHECK-NEXT: .cfi_offset %rbp, -16
> ; CHECK-NEXT: movq %rsp, %rbp
> ; CHECK-NEXT: :
> -; CHECK-NEXT: .cfi_def_cfa_register 6
> +; CHECK-NEXT: .cfi_def_cfa_register %rbp
> ; CHECK-NEXT: popq %rbp
> ; CHECK-NEXT: ret
>
> Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132317&r1=132316&r2=132317&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon May 30 15:20:15 2011
> @@ -80,6 +80,8 @@
> << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
> << " virtual int getDwarfRegNumFull(unsigned RegNum, "
> << "unsigned Flavour) const;\n"
> + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
> + << "unsigned Flavour) const;\n"
> << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
> << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
> << " { return false; }\n"
> @@ -989,6 +991,33 @@
> for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
> I->second.push_back(-1);
>
> + // Emit reverse information about the dwarf register numbers.
> + OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
> + << "unsigned Flavour) const {\n"
> + << " switch (Flavour) {\n"
> + << " default:\n"
> + << " assert(0 && \"Unknown DWARF flavour\");\n"
> + << " return -1;\n";
> +
> + for (unsigned i = 0, e = maxLength; i != e; ++i) {
> + OS << " case " << i << ":\n"
> + << " switch (DwarfRegNum) {\n"
> + << " default:\n"
> + << " assert(0 && \"Invalid DwarfRegNum\");\n"
> + << " return -1;\n";
> +
> + for (DwarfRegNumsMapTy::iterator
> + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
> + int DwarfRegNo = I->second[i];
> + if (DwarfRegNo >= 0)
> + OS << " case " << DwarfRegNo << ":\n"
> + << " return " << getQualifiedName(I->first) << ";\n";
> + }
> + OS << " };\n";
> + }
> +
> + OS << " };\n}\n\n";
> +
> for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
> Record *Reg = Regs[i].TheDef;
> const RecordVal *V = Reg->getValue("DwarfAlias");
>
>
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