[llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

Rotem, Nadav nadav.rotem at intel.com
Tue May 10 10:44:10 PDT 2011

There is no v2i64 sra instruction. I will make the corrections and commit. 


-----Original Message-----
From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands
Sent: Tuesday, May 10, 2011 15:44
To: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

Hi Nadav,

> +    setOperationAction(ISD::SRA,               MVT::v4i32, Custom);
> +    setOperationAction(ISD::SRA,               MVT::v8i16, Custom);

so there is no v2i64 arithmetic right shift?

> +  // Must have SSE2
> +  if(! Subtarget->hasSSE2()) return SDValue();

There should be a space between "if" and "(" and no space after "!".  This
problem occurs also in the SSE 4.1 test.

> -  if (VT == MVT::v4i32) {
> +  // Optimize shl/srl with constant shift amount

There should be a full stop at the end of the comment.  The comment doesn't
mention sra but it is handled too.

Otherwise it looks OK to me.

Ciao, Duncan.
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