[llvm-commits] [dragonegg] r131083 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp

[Duncan Sands]

Author: baldrick
Date: Mon May  9 06:19:49 2011
New Revision: 131083

URL: http://llvm.org/viewvc/llvm-project?rev=131083&view=rev
Log:
Add support for VEC_EXTRACT_EVEN_EXPR, VEC_EXTRACT_ODD_EXPR,
VEC_INTERLEAVE_HIGH_EXPR and VEC_INTERLEAVE_LOW_EXPR.  These
may be produced by the GCC vectorizer when GCC optimizations
are enabled.

Modified:
    dragonegg/trunk/include/dragonegg/Internals.h
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/include/dragonegg/Internals.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=131083&r1=131082&r2=131083&view=diff
==============================================================================
--- dragonegg/trunk/include/dragonegg/Internals.h (original)
+++ dragonegg/trunk/include/dragonegg/Internals.h Mon May  9 06:19:49 2011
@@ -717,6 +717,10 @@
                                 tree_node *op1);
   Value *EmitReg_TRUNC_DIV_EXPR(tree_node *op0, tree_node *op1, bool isExact);
   Value *EmitReg_TRUNC_MOD_EXPR(tree_node *op0, tree_node *op1);
+  Value *EmitReg_VEC_EXTRACT_EVEN_EXPR(tree_node *op0, tree_node *op1);
+  Value *EmitReg_VEC_EXTRACT_ODD_EXPR(tree_node *op0, tree_node *op1);
+  Value *EmitReg_VEC_INTERLEAVE_HIGH_EXPR(tree_node *op0, tree_node *op1);
+  Value *EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree_node *op0, tree_node *op1);
 
   Value *EmitLoadOfLValue(tree_node *exp);
   Value *EmitOBJ_TYPE_REF(tree_node *exp);

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=131083&r1=131082&r2=131083&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Mon May  9 06:19:49 2011
@@ -6944,6 +6944,56 @@
     Builder.CreateURem(LHS, RHS) : Builder.CreateSRem(LHS, RHS);
 }
 
+Value *TreeToLLVM::EmitReg_VEC_EXTRACT_EVEN_EXPR(tree op0, tree op1) {
+  Value *LHS = EmitRegister(op0);
+  Value *RHS = EmitRegister(op1);
+  unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op0));
+  SmallVector<Constant*, 16> Mask;
+  Mask.reserve(Length);
+  for (unsigned i = 0; i != Length; ++i)
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), 2*i));
+  return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
+}
+
+Value *TreeToLLVM::EmitReg_VEC_EXTRACT_ODD_EXPR(tree op0, tree op1) {
+  Value *LHS = EmitRegister(op0);
+  Value *RHS = EmitRegister(op1);
+  unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op0));
+  SmallVector<Constant*, 16> Mask;
+  Mask.reserve(Length);
+  for (unsigned i = 0; i != Length; ++i)
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), 2*i+1));
+  return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
+}
+
+Value *TreeToLLVM::EmitReg_VEC_INTERLEAVE_HIGH_EXPR(tree op0, tree op1) {
+  Value *LHS = EmitRegister(op0);
+  Value *RHS = EmitRegister(op1);
+  unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op0));
+  assert(!(Length & 1) && "Expected an even number of vector elements!");
+  SmallVector<Constant*, 16> Mask;
+  Mask.reserve(Length);
+  for (unsigned i = Length/2; i != Length; ++i) {
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), i));
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + i));
+  }
+  return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
+}
+
+Value *TreeToLLVM::EmitReg_VEC_INTERLEAVE_LOW_EXPR(tree op0, tree op1) {
+  Value *LHS = EmitRegister(op0);
+  Value *RHS = EmitRegister(op1);
+  unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op0));
+  assert(!(Length & 1) && "Expected an even number of vector elements!");
+  SmallVector<Constant*, 16> Mask;
+  Mask.reserve(Length);
+  for (unsigned i = 0, e = Length/2; i != e; ++i) {
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), i));
+    Mask.push_back(ConstantInt::get(Type::getInt32Ty(Context), Length + i));
+  }
+  return Builder.CreateShuffleVector(LHS, RHS, ConstantVector::get(Mask));
+}
+
 
 //===----------------------------------------------------------------------===//
 //                        ... Exception Handling ...
@@ -7800,7 +7850,7 @@
   Value *RHS = 0;
   switch (code) {
   default:
-    DieAbjectly("Unhandled GIMPLE assignment!", stmt);
+    DieAbjectly("Unsupported GIMPLE assignment!", stmt);
 
   // Unary expressions.
   case ABS_EXPR:
@@ -7901,6 +7951,14 @@
     RHS = EmitReg_TruthOp(type, rhs1, rhs2, Instruction::Or); break;
   case TRUTH_XOR_EXPR:
     RHS = EmitReg_TruthOp(type, rhs1, rhs2, Instruction::Xor); break;
+  case VEC_EXTRACT_EVEN_EXPR:
+    RHS = EmitReg_VEC_EXTRACT_EVEN_EXPR(rhs1, rhs2); break;
+  case VEC_EXTRACT_ODD_EXPR:
+    RHS = EmitReg_VEC_EXTRACT_ODD_EXPR(rhs1, rhs2); break;
+  case VEC_INTERLEAVE_HIGH_EXPR:
+    RHS = EmitReg_VEC_INTERLEAVE_HIGH_EXPR(rhs1, rhs2); break;
+  case VEC_INTERLEAVE_LOW_EXPR:
+    RHS = EmitReg_VEC_INTERLEAVE_LOW_EXPR(rhs1, rhs2); break;
   }
 
   assert(RHS->getType() == getRegType(type) && "RHS has wrong type!");