[llvm-commits] [llvm] r130033 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp

[Owen Anderson]

Author: resistor
Date: Fri Apr 22 18:38:06 2011
New Revision: 130033

URL: http://llvm.org/viewvc/llvm-project?rev=130033&view=rev
Log:
Teach FastISel to deal with instructions that have two immediate operands.

Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=130033&r1=130032&r2=130033&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Fri Apr 22 18:38:06 2011
@@ -288,7 +288,12 @@
   unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
                           const TargetRegisterClass *RC,
                           uint64_t Imm);
-  
+
+  /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
+  unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
+                          const TargetRegisterClass *RC,
+                          uint64_t Imm1, uint64_t Imm2);
+
   /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
   /// from a specified index of a superregister to a specified type.
   unsigned FastEmitInst_extractsubreg(MVT RetVT,

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=130033&r1=130032&r2=130033&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Apr 22 18:38:06 2011
@@ -338,18 +338,18 @@
       if (Op1 == 0) return false;
 
       bool Op1IsKill = hasTrivialKill(I->getOperand(1));
-      
+
       unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
                                         Op1IsKill, CI->getZExtValue(),
                                         VT.getSimpleVT());
       if (ResultReg == 0) return false;
-      
+
       // We successfully emitted code for the given LLVM Instruction.
       UpdateValueMap(I, ResultReg);
       return true;
     }
-  
-  
+
+
   unsigned Op0 = getRegForValue(I->getOperand(0));
   if (Op0 == 0)   // Unhandled operand. Halt "fast" selection and bail.
     return false;
@@ -359,7 +359,7 @@
   // Check if the second operand is a constant and handle it appropriately.
   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
     uint64_t Imm = CI->getZExtValue();
-    
+
     // Transform "sdiv exact X, 8" -> "sra X, 3".
     if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
         cast<BinaryOperator>(I)->isExact() &&
@@ -367,11 +367,11 @@
       Imm = Log2_64(Imm);
       ISDOpcode = ISD::SRA;
     }
-    
+
     unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
                                       Op0IsKill, Imm, VT.getSimpleVT());
     if (ResultReg == 0) return false;
-    
+
     // We successfully emitted code for the given LLVM Instruction.
     UpdateValueMap(I, ResultReg);
     return true;
@@ -553,7 +553,7 @@
     EVT VT = TLI.getValueType(I->getType());
     if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand)
       break;
-    
+
     assert(FuncInfo.MBB->isLandingPad() &&
            "Call to eh.exception not in landing pad!");
     unsigned Reg = TLI.getExceptionAddressRegister();
@@ -995,13 +995,13 @@
     Opcode = ISD::SRL;
     Imm = Log2_64(Imm);
   }
-  
+
   // Horrible hack (to be removed), check to make sure shift amounts are
   // in-range.
   if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
       Imm >= VT.getSizeInBits())
     return 0;
-  
+
   // First check if immediate type is legal. If not, we can't use the ri form.
   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
   if (ResultReg != 0)
@@ -1219,6 +1219,23 @@
   return ResultReg;
 }
 
+unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
+                                  const TargetRegisterClass *RC,
+                                  uint64_t Imm1, uint64_t Imm2) {
+  unsigned ResultReg = createResultReg(RC);
+  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
+
+  if (II.getNumDefs() >= 1)
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
+      .addImm(Imm1).addImm(Imm2);
+  else {
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
+            ResultReg).addReg(II.ImplicitDefs[0]);
+  }
+  return ResultReg;
+}
+
 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
                                               unsigned Op0, bool Op0IsKill,
                                               uint32_t Idx) {