[llvm-commits] Source register same as write-back base

[Joe Abbey]

> Do you know exactly which instructions have this constraint?

Yep,

Every store instruction appears to have at least one encoding which has
the unpredictable constraint.  The two that are currently tripping me up
are:

STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]
STR<c> <Rt>,[<Rn>],#+/-<imm12>

But here's an exhaustive list pulled from ARM(r) Architecture Reference
Manual ARM(r)v7-A and ARM(r)v7-R edition.

A8.6.193 STR (immediate, Thumb)
==============================
Encoding T4 ARMv6T2, ARMv7
STR<c> <Rt>,[<Rn>,#-<imm8>]
STR<c> <Rt>,[<Rn>],#+/-<imm8>
STR<c> <Rt>,[<Rn>,#+/-<imm8>]!
if t == 15 || (wback && n == t) then UNPREDICTABLE;

A8.6.194 STR (immediate, ARM)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]
STR<c> <Rt>,[<Rn>],#+/-<imm12>
STR<c> <Rt>,[<Rn>,#+/-<imm12>]!
if wback && (n == 15 || n == t) then UNPREDICTABLE;

A8.6.195 STR (register)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}
STR<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
if wback && (n == 15 || n == t) then UNPREDICTABLE;
if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;

A8.6.196 STRB (immediate, Thumb)
==============================
Encoding T3 ARMv6T2, ARMv7
STRB<c> <Rt>,[<Rn>,#-<imm8>]
STRB<c> <Rt>,[<Rn>],#+/-<imm8>
STRB<c> <Rt>,[<Rn>,#+/-<imm8>]!
if BadReg(t) || (wback && n == t) then UNPREDICTABLE;

A8.6.197 STRB (immediate, ARM)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]
STRB<c> <Rt>,[<Rn>],#+/-<imm12>
STRB<c> <Rt>,[<Rn>,#+/-<imm12>]!
if wback && (n == 15 || n == t) then UNPREDICTABLE;

A8.6.198 STRB (register)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!}
STRB<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
if wback && (n == 15 || n == t) then UNPREDICTABLE;
if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;

A8.6.199 STRBT
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRBT<c> <Rt>,[<Rn>],#+/-<imm12>
if t == 15 || n == 15 || n == t then UNPREDICTABLE;

Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;
if ArchVersion() < 6 && m == n then UNPREDICTABLE;

A8.6.200 STRD (immediate)
==============================
Encoding T1 ARMv6T2, ARMv7
STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm>}]
STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm>
STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]!
if wback && (n == t || n == t2) then UNPREDICTABLE;

Encoding A1 ARMv5TE*, ARMv6*, ARMv7
STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;

A8.6.201 STRD (register)
==============================
Encoding A1 ARMv5TE*, ARMv6*, ARMv7
STRD<c> <Rt>,<Rt2>,[<Rn>,+/-<Rm>]{!}
STRD<c> <Rt>,<Rt2>,[<Rn>],+/-<Rm>
if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;

A8.6.202 STREX
==============================
Encoding T1 ARMv6T2, ARMv7
STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
if d == n || d == t then UNPREDICTABLE;

Encoding A1 ARMv6*, ARMv7
STREX<c> <Rd>,<Rt>,[<Rn>]
if d == n || d == t then UNPREDICTABLE;

A8.6.203 STREXB
==============================
Encoding T1 ARMv7
STREXB<c> <Rd>,<Rt>,[<Rn>]
if d == n || d == t then UNPREDICTABLE;

Encoding A1 ARMv6K, ARMv7
STREXB<c> <Rd>,<Rt>,[<Rn>]
if d == n || d == t then UNPREDICTABLE;

A8.6.204 STREXD
==============================
Encoding T1 ARMv7
STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
if d == n || d == t || d == t2 then UNPREDICTABLE;

Encoding A1 ARMv6K, ARMv7
STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
if d == n || d == t || d == t2 then UNPREDICTABLE;

A8.6.205 STREXH
==============================
Encoding T1 ARMv7
STREXH<c> <Rd>,<Rt>,[<Rn>]
if d == n || d == t then UNPREDICTABLE;

Encoding A1 ARMv6K, ARMv7
STREXH<c> <Rd>,<Rt>,[<Rn>]
if d == n || d == t then UNPREDICTABLE;

A8.6.206 STRH (immediate, Thumb)
==============================
Encoding T3 ARMv6T2, ARMv7
STRH<c> <Rt>,[<Rn>,#-<imm8>]
STRH<c> <Rt>,[<Rn>],#+/-<imm8>
STRH<c> <Rt>,[<Rn>,#+/-<imm8>]!
if BadReg(t) || (wback && n == t) then UNPREDICTABLE;

A8.6.207 STRH (immediate, ARM)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]
STRH<c> <Rt>,[<Rn>],#+/-<imm8>
STRH<c> <Rt>,[<Rn>,#+/-<imm8>]!
if wback && (n == 15 || n == t) then UNPREDICTABLE;

A8.6.208 STRH (register)
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!}
STRH<c> <Rt>,[<Rn>],+/-<Rm>
if wback && (n == 15 || n == t) then UNPREDICTABLE;
if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE;

A8.6.209 STRHT
==============================
Encoding A1 ARMv6T2, ARMv7
STRHT<c> <Rt>, [<Rn>] {, #+/-<imm8>}
if t == 15 || n == 15 || n == t then UNPREDICTABLE;

Encoding A2 ARMv6T2, ARMv7
STRHT<c> <Rt>, [<Rn>], +/-<Rm>
if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;

A8.6.210 STRT
==============================
Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRT<c> <Rt>, [<Rn>] {, +/-<imm12>}
if n == 15 || n == t then UNPREDICTABLE;

Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7
STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>}
if n == 15 || n == t || m == 15 then UNPREDICTABLE;
if ArchVersion() < 6 && m == n then UNPREDICTABLE;

Cheers,

Joe