[llvm-commits] Source register same as write-back base

[Jakob Stoklund Olesen]

On Apr 12, 2011, at 11:36 AM, Joe Abbey wrote:

> Yes this is the same restriction as armV5 MUL, and it is likely the case
> that all hardware implementations behave correctly.  
> 
> However, this restriction is documented in ARMv5 & ARMv7:
> 
> DD101001 A4.1.99
> If <addressing_mode> specifies base register write-back, and the same
> register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE.
> 
> DDI0406B A8.6.194
> if wback && (n == 15 || n == t) then UNPREDICTABLE;
> 
> I see that in ARMInstrInfo.td MULv5 considers $Rd to be earlyclobber.  
> 
> Could a similar pattern of making $Rt earlyclobber be applied in the
> store instrucitons? 

Yes, it could.

However, that would cause the fast register allocator to take the slow path for store instructions, and as you can imagine, they are prevalent in debug code.

I would rather not slow down register allocation in order to work around a problem that only shows up as an assembler warning.

What kind of code is producing this instruction? It seems odd to store a pointer to itself:

  *p++ = p;

/jakob