[llvm-commits] [llvm] r128892 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMInstrInfo.td
Jim Grosbach
grosbach at apple.com
Tue Apr 5 11:13:53 PDT 2011
Nice! Thanks for doing this.
Couple of comments inline.
On Apr 5, 2011, at 10:24 AM, Owen Anderson wrote:
> Author: resistor
> Date: Tue Apr 5 12:24:25 2011
> New Revision: 128892
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128892&view=rev
> Log:
> Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
Would it perhaps be better to handle these via a custom inserter instead of in the expansion pass? That way the real instruction is added earlier in translation and all of the machine instr passes will see them, not the pseudos. The expand-pseudos pass is a post-regalloc lowering.
This should have the added benefit of exposing these instructions to the if-conversion pass since they are predicable (and the pseudos are not).
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=128892&r1=128891&r2=128892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Apr 5 12:24:25 2011
> @@ -55,6 +55,7 @@
> void ExpandVLD(MachineBasicBlock::iterator &MBBI);
> void ExpandVST(MachineBasicBlock::iterator &MBBI);
> void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
> + void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
> void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
> unsigned Opc, bool IsExt, unsigned NumRegs);
> void ExpandMOV32BitImm(MachineBasicBlock &MBB,
> @@ -629,6 +630,43 @@
> MI.eraseFromParent();
> }
>
> +void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
> + MachineInstr &MI = *MBBI;
> + MachineBasicBlock &MBB = *MI.getParent();
> + unsigned OldOpc = MI.getOpcode();
> + unsigned Opc = 0;
> + switch (OldOpc) {
> + case ARM::ADCSSrr:
> + Opc = ARM::ADCrr;
> + break;
> + case ARM::ADCSSri:
> + Opc = ARM::ADCri;
> + break;
> + case ARM::ADCSSrs:
> + Opc = ARM::ADCrs;
> + break;
> + case ARM::SBCSSrr:
> + Opc = ARM::SBCrr;
> + break;
> + case ARM::SBCSSri:
> + Opc = ARM::SBCri;
> + break;
> + case ARM::SBCSSrs:
> + Opc = ARM::SBCrs;
> + break;
> + default:
> + llvm_unreachable("Unknown opcode?");
> + }
> +
> + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
> + MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
The predicate operand is actually two operands, a immediate (the condition code) and a register (either reg0 for unpredicated or CPSR for predicated).
> + MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
Likewise, the 's' bit operand is a register operand of reg0 or CPSR.
> + for (unsigned i = 0; i < MI.getNumOperands(); ++i)
> + MIB.addOperand(MI.getOperand(i));
The predicate and 's' bit operands come at the end of the operand list, not the beginning, right? So this should happen before adding the predicate and 's' bit operands.
> + TransferImpOps(MI, MIB, MIB);
> + MI.eraseFromParent();
> +}
> +
> void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator &MBBI) {
> MachineInstr &MI = *MBBI;
> @@ -941,6 +979,15 @@
> ExpandMOV32BitImm(MBB, MBBI);
> return true;
>
> + case ARM::ADCSSri:
> + case ARM::ADCSSrr:
> + case ARM::ADCSSrs:
> + case ARM::SBCSSri:
> + case ARM::SBCSSrr:
> + case ARM::SBCSSrs:
> + ExpandSBitOp(MBBI);
> + return true;
> +
> case ARM::VMOVQQ: {
> unsigned DstReg = MI.getOperand(0).getReg();
> bool DstIsDead = MI.getOperand(0).isDead();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128892&r1=128891&r2=128892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr 5 12:24:25 2011
> @@ -938,50 +938,18 @@
> let isCodeGenOnly = 1, Defs = [CPSR] in {
> multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
> bit Commutable = 0> {
> - def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> - DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
> + def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> + Size4Bytes, IIC_iALUi,
> [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
> - Requires<[IsARM]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> imm;
> - let Inst{31-27} = 0b1110; // non-predicated
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> - let Inst{11-0} = imm;
> - let Inst{20} = 1;
> - let Inst{25} = 1;
> - }
> - def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> - DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
> + Requires<[IsARM]>;
> + def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> + Size4Bytes, IIC_iALUr,
> [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
> - Requires<[IsARM]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<4> Rm;
> - let Inst{31-27} = 0b1110; // non-predicated
> - let Inst{11-4} = 0b00000000;
> - let isCommutable = Commutable;
> - let Inst{3-0} = Rm;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> - let Inst{20} = 1;
> - let Inst{25} = 0;
> - }
> - def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> - DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
> + Requires<[IsARM]>;
> + def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> + Size4Bytes, IIC_iALUsr,
> [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
> - Requires<[IsARM]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> shift;
> - let Inst{31-27} = 0b1110; // non-predicated
> - let Inst{11-0} = shift;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> - let Inst{20} = 1;
> - let Inst{25} = 0;
> - }
> + Requires<[IsARM]>;
> }
> }
> }
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list