[llvm-commits] [llvm] r128587 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td
Evan Cheng
evan.cheng at apple.com
Wed Mar 30 17:20:31 PDT 2011
On Mar 30, 2011, at 4:45 PM, Owen Anderson wrote:
> Author: resistor
> Date: Wed Mar 30 18:45:29 2011
> New Revision: 128587
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128587&view=rev
> Log:
> Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
Very nice!
Evan
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=128587&r1=128586&r2=128587&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Mar 30 18:45:29 2011
> @@ -1682,7 +1682,8 @@
> }
>
> // NEON 3 vector register format.
> -class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> +
> +class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> dag oops, dag iops, Format f, InstrItinClass itin,
> string opc, string dt, string asm, string cstr, list<dag> pattern>
> : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
> @@ -1692,6 +1693,13 @@
> let Inst{11-8} = op11_8;
> let Inst{6} = op6;
> let Inst{4} = op4;
> +}
> +
> +class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> + dag oops, dag iops, Format f, InstrItinClass itin,
> + string opc, string dt, string asm, string cstr, list<dag> pattern>
> + : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
> + oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
>
> // Instruction operands.
> bits<5> Vd;
> @@ -1706,6 +1714,47 @@
> let Inst{5} = Vm{4};
> }
>
> +class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> + dag oops, dag iops, Format f, InstrItinClass itin,
> + string opc, string dt, string asm, string cstr, list<dag> pattern>
> + : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
> + oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
> +
> + // Instruction operands.
> + bits<5> Vd;
> + bits<5> Vn;
> + bits<5> Vm;
> + bit lane;
> +
> + let Inst{15-12} = Vd{3-0};
> + let Inst{22} = Vd{4};
> + let Inst{19-16} = Vn{3-0};
> + let Inst{7} = Vn{4};
> + let Inst{3-0} = Vm{3-0};
> + let Inst{5} = lane;
> +}
> +
> +class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
> + dag oops, dag iops, Format f, InstrItinClass itin,
> + string opc, string dt, string asm, string cstr, list<dag> pattern>
> + : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
> + oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
> +
> + // Instruction operands.
> + bits<5> Vd;
> + bits<5> Vn;
> + bits<5> Vm;
> + bits<2> lane;
> +
> + let Inst{15-12} = Vd{3-0};
> + let Inst{22} = Vd{4};
> + let Inst{19-16} = Vn{3-0};
> + let Inst{7} = Vn{4};
> + let Inst{2-0} = Vm{2-0};
> + let Inst{5} = lane{1};
> + let Inst{3} = lane{0};
> +}
> +
> // Same as N3V except it doesn't have a data type suffix.
> class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
> bit op4,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=128587&r1=128586&r2=128587&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Mar 30 18:45:29 2011
> @@ -1799,7 +1799,7 @@
> class N3VDSL<bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType Ty, SDNode ShOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (Ty DPR:$Vd),
> @@ -1809,7 +1809,7 @@
> }
> class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
> string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
> [(set (Ty DPR:$Vd),
> @@ -1839,7 +1839,7 @@
> class N3VQSL<bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, SDNode ShOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (ResTy QPR:$Vd),
> @@ -1850,7 +1850,7 @@
> }
> class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, SDNode ShOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
> [(set (ResTy QPR:$Vd),
> @@ -1872,7 +1872,7 @@
> }
> class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (Ty DPR:$Vd),
> @@ -1883,7 +1883,7 @@
> }
> class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (Ty DPR:$Vd),
> @@ -1913,7 +1913,7 @@
> class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (ResTy QPR:$Vd),
> @@ -1925,7 +1925,7 @@
> class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (ResTy QPR:$Vd),
> @@ -1957,7 +1957,7 @@
> class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd),
> (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -1970,7 +1970,7 @@
> class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType Ty, SDNode MulOp, SDNode ShOp>
> - : N3V<0, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
> (outs DPR:$Vd),
> (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -1992,7 +1992,7 @@
> class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
> SDPatternOperator MulOp, SDPatternOperator ShOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd),
> (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -2006,7 +2006,7 @@
> string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy,
> SDNode MulOp, SDNode ShOp>
> - : N3V<1, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd),
> (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -2067,7 +2067,7 @@
> class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
> + : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
> (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
> @@ -2079,7 +2079,7 @@
> class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
> + : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
> (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
> @@ -2114,7 +2114,7 @@
> class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd),
> (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -2127,7 +2127,7 @@
> class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd),
> (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin,
> @@ -2162,7 +2162,7 @@
> class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType TyQ, ValueType TyD, SDNode OpNode>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set QPR:$Vd,
> @@ -2171,7 +2171,7 @@
> class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType TyQ, ValueType TyD, SDNode OpNode>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set QPR:$Vd,
> @@ -2217,7 +2217,7 @@
> class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
> string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (ResTy QPR:$Vd),
> @@ -2227,7 +2227,7 @@
> class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
> InstrItinClass itin, string OpcodeStr, string Dt,
> ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
> - : N3V<op24, 1, op21_20, op11_8, 1, 0,
> + : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
> (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
> NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
> [(set (ResTy QPR:$Vd),
>
>
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