[llvm-commits] [llvm] r128461 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt
Evan Cheng
evan.cheng at apple.com
Tue Mar 29 10:42:58 PDT 2011
Hi Owen,
Does this patch work?
Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);
If Mode is ARM_AM::db, getLoadStoreMultipleOpcode() can return 0 and this would not work right?
Evan
On Mar 29, 2011, at 9:45 AM, Owen Anderson wrote:
> Author: resistor
> Date: Tue Mar 29 11:45:53 2011
> New Revision: 128461
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128461&view=rev
> Log:
> Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Mar 29 11:45:53 2011
> @@ -1789,9 +1789,7 @@
> llvm_unreachable("Unexpected multi-uops instruction!");
> break;
> case ARM::VLDMQIA:
> - case ARM::VLDMQDB:
> case ARM::VSTMQIA:
> - case ARM::VSTMQDB:
> return 2;
>
> // The number of uOps for load / store multiple are determined by the number
> @@ -1805,19 +1803,15 @@
> // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
> // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
> case ARM::VLDMDIA:
> - case ARM::VLDMDDB:
> case ARM::VLDMDIA_UPD:
> case ARM::VLDMDDB_UPD:
> case ARM::VLDMSIA:
> - case ARM::VLDMSDB:
> case ARM::VLDMSIA_UPD:
> case ARM::VLDMSDB_UPD:
> case ARM::VSTMDIA:
> - case ARM::VSTMDDB:
> case ARM::VSTMDIA_UPD:
> case ARM::VSTMDDB_UPD:
> case ARM::VSTMSIA:
> - case ARM::VSTMSDB:
> case ARM::VSTMSIA_UPD:
> case ARM::VSTMSDB_UPD: {
> unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
> @@ -1907,7 +1901,6 @@
> switch (DefTID.getOpcode()) {
> default: break;
> case ARM::VLDMSIA:
> - case ARM::VLDMSDB:
> case ARM::VLDMSIA_UPD:
> case ARM::VLDMSDB_UPD:
> isSLoad = true;
> @@ -1983,7 +1976,6 @@
> switch (UseTID.getOpcode()) {
> default: break;
> case ARM::VSTMSIA:
> - case ARM::VSTMSDB:
> case ARM::VSTMSIA_UPD:
> case ARM::VSTMSDB_UPD:
> isSStore = true;
> @@ -2054,11 +2046,9 @@
> break;
>
> case ARM::VLDMDIA:
> - case ARM::VLDMDDB:
> case ARM::VLDMDIA_UPD:
> case ARM::VLDMDDB_UPD:
> case ARM::VLDMSIA:
> - case ARM::VLDMSDB:
> case ARM::VLDMSIA_UPD:
> case ARM::VLDMSDB_UPD:
> DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
> @@ -2097,11 +2087,9 @@
> break;
>
> case ARM::VSTMDIA:
> - case ARM::VSTMDDB:
> case ARM::VSTMDIA_UPD:
> case ARM::VSTMDDB_UPD:
> case ARM::VSTMSIA:
> - case ARM::VSTMSDB:
> case ARM::VSTMSIA_UPD:
> case ARM::VSTMSDB_UPD:
> UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
> @@ -2312,9 +2300,7 @@
> default:
> return ItinData->getStageLatency(get(Opcode).getSchedClass());
> case ARM::VLDMQIA:
> - case ARM::VLDMQDB:
> case ARM::VSTMQIA:
> - case ARM::VSTMQDB:
> return 2;
> }
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Mar 29 11:45:53 2011
> @@ -967,9 +967,8 @@
> return true;
> }
>
> - case ARM::VLDMQIA:
> - case ARM::VLDMQDB: {
> - unsigned NewOpc = (Opcode == ARM::VLDMQIA) ? ARM::VLDMDIA : ARM::VLDMDDB;
> + case ARM::VLDMQIA: {
> + unsigned NewOpc = ARM::VLDMDIA;
> MachineInstrBuilder MIB =
> BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
> unsigned OpIdx = 0;
> @@ -998,9 +997,8 @@
> return true;
> }
>
> - case ARM::VSTMQIA:
> - case ARM::VSTMQDB: {
> - unsigned NewOpc = (Opcode == ARM::VSTMQIA) ? ARM::VSTMDIA : ARM::VSTMDDB;
> + case ARM::VSTMQIA: {
> + unsigned NewOpc = ARM::VSTMDIA;
> MachineInstrBuilder MIB =
> BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
> unsigned OpIdx = 0;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Mar 29 11:45:53 2011
> @@ -146,10 +146,6 @@
> : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
> IIC_fpLoad_m, "",
> [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
> -def VLDMQDB
> - : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
> - IIC_fpLoad_m, "",
> - [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
>
> // Use VSTM to store a Q register as a D register pair.
> // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
> @@ -157,10 +153,6 @@
> : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
> IIC_fpStore_m, "",
> [(store (v2f64 QPR:$src), GPR:$Rn)]>;
> -def VSTMQDB
> - : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
> - IIC_fpStore_m, "",
> - [(store (v2f64 QPR:$src), GPR:$Rn)]>;
>
> // Classes for VLD* pseudo-instructions with multi-register operands.
> // These are expanded to real instructions after register allocation.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Mar 29 11:45:53 2011
> @@ -101,14 +101,6 @@
> let Inst{21} = 1; // Writeback
> let Inst{20} = L_bit;
> }
> - def DDB :
> - AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
> - IndexModeNone, itin,
> - !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
> - let Inst{24-23} = 0b10; // Decrement Before
> - let Inst{21} = 0; // No writeback
> - let Inst{20} = L_bit;
> - }
> def DDB_UPD :
> AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
> IndexModeUpd, itin_upd,
> @@ -143,18 +135,6 @@
> // VFP pipelines.
> let D = VFPNeonDomain;
> }
> - def SDB :
> - AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
> - IndexModeNone, itin,
> - !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
> - let Inst{24-23} = 0b10; // Decrement Before
> - let Inst{21} = 0; // No writeback
> - let Inst{20} = L_bit;
> -
> - // Some single precision VFP instructions may be executed on both NEON and
> - // VFP pipelines.
> - let D = VFPNeonDomain;
> - }
> def SDB_UPD :
> AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
> IndexModeUpd, itin_upd,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Mar 29 11:45:53 2011
> @@ -79,7 +79,7 @@
> unsigned Position;
> MachineBasicBlock::iterator MBBI;
> bool Merged;
> - MemOpQueueEntry(int o, unsigned r, bool k, unsigned p,
> + MemOpQueueEntry(int o, unsigned r, bool k, unsigned p,
> MachineBasicBlock::iterator i)
> : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
> };
> @@ -174,7 +174,7 @@
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VLDMSIA;
> - case ARM_AM::db: return ARM::VLDMSDB;
> + case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
> }
> break;
> case ARM::VSTRS:
> @@ -182,7 +182,7 @@
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VSTMSIA;
> - case ARM_AM::db: return ARM::VSTMSDB;
> + case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
> }
> break;
> case ARM::VLDRD:
> @@ -190,7 +190,7 @@
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VLDMDIA;
> - case ARM_AM::db: return ARM::VLDMDDB;
> + case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
> }
> break;
> case ARM::VSTRD:
> @@ -198,7 +198,7 @@
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VSTMDIA;
> - case ARM_AM::db: return ARM::VSTMDDB;
> + case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
> }
> break;
> }
> @@ -246,13 +246,9 @@
> case ARM::t2LDMDB_UPD:
> case ARM::t2STMDB:
> case ARM::t2STMDB_UPD:
> - case ARM::VLDMSDB:
> case ARM::VLDMSDB_UPD:
> - case ARM::VSTMSDB:
> case ARM::VSTMSDB_UPD:
> - case ARM::VLDMDDB:
> case ARM::VLDMDDB_UPD:
> - case ARM::VSTMDDB:
> case ARM::VSTMDDB_UPD:
> return ARM_AM::db;
>
> @@ -567,14 +563,10 @@
> case ARM::t2STMIA:
> case ARM::t2STMDB:
> case ARM::VLDMSIA:
> - case ARM::VLDMSDB:
> case ARM::VSTMSIA:
> - case ARM::VSTMSDB:
> return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4;
> case ARM::VLDMDIA:
> - case ARM::VLDMDDB:
> case ARM::VSTMDIA:
> - case ARM::VSTMDDB:
> return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8;
> }
> }
> @@ -624,7 +616,6 @@
> }
> break;
> case ARM::VLDMSIA:
> - case ARM::VLDMSDB:
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VLDMSIA_UPD;
> @@ -632,7 +623,6 @@
> }
> break;
> case ARM::VLDMDIA:
> - case ARM::VLDMDDB:
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VLDMDIA_UPD;
> @@ -640,7 +630,6 @@
> }
> break;
> case ARM::VSTMSIA:
> - case ARM::VSTMSDB:
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VSTMSIA_UPD;
> @@ -648,7 +637,6 @@
> }
> break;
> case ARM::VSTMDIA:
> - case ARM::VSTMDDB:
> switch (Mode) {
> default: llvm_unreachable("Unhandled submode!");
> case ARM_AM::ia: return ARM::VSTMDIA_UPD;
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Mar 29 11:45:53 2011
> @@ -1123,7 +1123,7 @@
> case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
> case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
> return true;
> - }
> + }
> }
>
> static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
> @@ -1610,7 +1610,7 @@
> // A8.6.295 vcvt (floating-point <-> integer)
> // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
> // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
> -//
> +//
> // A8.6.297 vcvt (floating-point and fixed-point)
> // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
> static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
> @@ -1832,9 +1832,9 @@
>
> OpIdx += 3;
>
> - bool isSPVFP = (Opcode == ARM::VLDMSIA || Opcode == ARM::VLDMSDB ||
> + bool isSPVFP = (Opcode == ARM::VLDMSIA ||
> Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
> - Opcode == ARM::VSTMSIA || Opcode == ARM::VSTMSDB ||
> + Opcode == ARM::VSTMSIA ||
> Opcode == ARM::VSTMSIA_UPD || Opcode == ARM::VSTMSDB_UPD);
> unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
>
> @@ -1848,7 +1848,7 @@
> // Apply some sanity checks before proceeding.
> if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16))
> return false;
> -
> +
> for (unsigned i = 0; i < Regs; ++i) {
> MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
> RegD + i)));
> @@ -2286,15 +2286,15 @@
> // n == 2 && type == 0b1001 -> DblSpaced = true
> if (Name.startswith("VST2") || Name.startswith("VLD2"))
> DblSpaced = slice(insn, 11, 8) == 9;
> -
> +
> // n == 3 && type == 0b0101 -> DblSpaced = true
> if (Name.startswith("VST3") || Name.startswith("VLD3"))
> DblSpaced = slice(insn, 11, 8) == 5;
> -
> +
> // n == 4 && type == 0b0001 -> DblSpaced = true
> if (Name.startswith("VST4") || Name.startswith("VLD4"))
> DblSpaced = slice(insn, 11, 8) == 1;
> -
> +
> }
> return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
> slice(insn, 21, 21) == 0, DblSpaced, B);
> @@ -2391,7 +2391,7 @@
> //
> // Vector Move Long:
> // Qd Dm
> -//
> +//
> // Vector Move Narrow:
> // Dd Qm
> //
> @@ -2533,7 +2533,7 @@
> assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
>
> // Add the imm operand.
> -
> +
> // VSHLL has maximum shift count as the imm, inferred from its size.
> unsigned Imm;
> switch (Opcode) {
> @@ -2646,7 +2646,7 @@
> // N3RegFrm.
> if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
> return true;
> -
> +
> // Dm = Inst{5:3-0} => NEON Rm
> // or
> // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
> @@ -3183,7 +3183,7 @@
>
> return false;
> }
> -
> +
> /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
> /// the possible Predicate and SBitModifier, to build the remaining MCOperand
> /// constituents.
>
> Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Mar 29 11:45:53 2011
> @@ -173,9 +173,6 @@
> # CHECK: vcmpe.f64 d8, #0
> 0xc0 0x8b 0xb5 0xee
>
> -# CHECK: vldmdb r2, {s7, s8, s9, s10, s11}
> -0x05 0x3a 0x52 0xed
> -
> # CHECK: strtvc r5, [r3], r0, lsr #20
> 0x30 0x5a 0xa3 0x76
>
>
> Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt?rev=128461&r1=128460&r2=128461&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VLDMSDB-arm.txt Tue Mar 29 11:45:53 2011
> @@ -1,4 +1,5 @@
> # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
> +# XFAIL: *
>
> # core registers out of range
> -0xa5 0xba 0x52 0xed
> +0xa5 0xba 0xd2 0xed
>
>
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