[llvm-commits] [llvm] r128283 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt

[Johnny Chen]

Author: johnny
Date: Fri Mar 25 12:03:12 2011
New Revision: 128283

URL: http://llvm.org/viewvc/llvm-project?rev=128283&view=rev
Log:
Also need to handle invalid imod values for CPS2p.

rdar://problem/9186136

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128283&r1=128282&r2=128283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Mar 25 12:03:12 2011
@@ -2965,8 +2965,10 @@
   // opcodes which match the same real instruction. This is needed since there's
   // no current handling of optional arguments. Fix here when a better handling
   // of optional arguments is implemented.
-  if (Opcode == ARM::CPS3p) {
-    // Let's reject impossible imod values by returning false.
+  if (Opcode == ARM::CPS3p) {   // M = 1
+    // Let's reject these impossible imod values by returning false:
+    // 1. (imod=0b01)
+    //
     // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an
     // invalid combination, so we just check for imod=0b00 here.
     if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
@@ -2977,13 +2979,18 @@
     NumOpsAdded = 3;
     return true;
   }
-  if (Opcode == ARM::CPS2p) {
+  if (Opcode == ARM::CPS2p) { // mode = 0, M = 0
+    // Let's reject these impossible imod values by returning false:
+    // 1. (imod=0b00,M=0)
+    // 2. (imod=0b01)
+    if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1)
+      return false;
     MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod
     MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6)));   // iflags
     NumOpsAdded = 2;
     return true;
   }
-  if (Opcode == ARM::CPS1p) {
+  if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1
     MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode
     NumOpsAdded = 1;
     return true;

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt?rev=128283&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt Fri Mar 25 12:03:12 2011
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# invalid imod value (0b01)
+0xc0 0x67 0x4 0xf1