[llvm-commits] [llvm] r128254 - in /llvm/trunk/lib: CodeGen/RegAllocLinearScan.cpp Target/ARM/ARMBaseRegisterInfo.cpp

Jakob Stoklund Olesen stoklund at 2pi.dk
Thu Mar 24 18:48:18 PDT 2011


Author: stoklund
Date: Thu Mar 24 20:48:18 2011
New Revision: 128254

URL: http://llvm.org/viewvc/llvm-project?rev=128254&view=rev
Log:
Ignore special ARM allocation hints for unexpected register classes.

Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=128254&r1=128253&r2=128254&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Mar 24 20:48:18 2011
@@ -1110,6 +1110,7 @@
   // list.
   if (physReg) {
     DEBUG(dbgs() <<  tri_->getName(physReg) << '\n');
+    assert(RC->contains(physReg) && "Invalid candidate");
     vrm_->assignVirt2Phys(cur->reg, physReg);
     addRegUse(physReg);
     active_.push_back(std::make_pair(cur, cur->begin()));

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=128254&r1=128253&r2=128254&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Mar 24 20:48:18 2011
@@ -448,6 +448,10 @@
     ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
   };
 
+  // We only support even/odd hints for GPR and rGPR.
+  if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
+    return std::make_pair(RC->allocation_order_begin(MF),
+                          RC->allocation_order_end(MF));
 
   if (HintType == ARMRI::RegPairEven) {
     if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)





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