[llvm-commits] [llvm] r128243 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/neon-tests.txt

Johnny Chen johnny.chen at apple.com
Thu Mar 24 15:04:39 PDT 2011


Author: johnny
Date: Thu Mar 24 17:04:39 2011
New Revision: 128243

URL: http://llvm.org/viewvc/llvm-project?rev=128243&view=rev
Log:
Handle the added VBICiv*i* NEON instructions, too.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128243&r1=128242&r2=128243&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Mar 24 17:04:39 2011
@@ -2302,6 +2302,7 @@
 
 // VMOV (immediate)
 //   Qd/Dd imm
+// VBIC (immediate)
 // VORR (immediate)
 //   Qd/Dd imm src(=Qd/Dd)
 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
@@ -2330,6 +2331,8 @@
   case ARM::VMOVv8i16:
   case ARM::VMVNv4i16:
   case ARM::VMVNv8i16:
+  case ARM::VBICiv4i16:
+  case ARM::VBICiv8i16:
   case ARM::VORRiv4i16:
   case ARM::VORRiv8i16:
     esize = ESize16;
@@ -2338,6 +2341,8 @@
   case ARM::VMOVv4i32:
   case ARM::VMVNv2i32:
   case ARM::VMVNv4i32:
+  case ARM::VBICiv2i32:
+  case ARM::VBICiv4i32:
   case ARM::VORRiv2i32:
   case ARM::VORRiv4i32:
     esize = ESize32;
@@ -2347,7 +2352,7 @@
     esize = ESize64;
     break;
   default:
-    assert(0 && "Unreachable code!");
+    assert(0 && "Unexpected opcode!");
     return false;
   }
 
@@ -2357,7 +2362,7 @@
 
   NumOpsAdded = 2;
 
-  // VORRiv*i* variants have an extra $src = $Vd to be filled in.
+  // VBIC/VORRiv*i* variants have an extra $src = $Vd to be filled in.
   if (NumOps >= 3 &&
       (OpInfo[2].RegClass == ARM::DPRRegClassID ||
        OpInfo[2].RegClass == ARM::QPRRegClassID)) {

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=128243&r1=128242&r2=128243&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Thu Mar 24 17:04:39 2011
@@ -65,3 +65,6 @@
 
 # CHECK:	vorr.i32	q15, #0x4F0000
 0x5f 0xe5 0xc4 0xf2
+
+# CHECK:	vbic.i32	q2, #0xA900
+0x79 0x53 0x82 0xf3





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