[llvm-commits] [llvm] r127913 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/rev.ll

[Evan Cheng]

A better fix might be to canonicalize (sext_inreg (or (srl $R, 8), (shl $R, 8)), i16) to (sra (bswap $R), 16). I'll implement that as soon as I have a chance.

Evan

On Mar 18, 2011, at 2:52 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Fri Mar 18 16:52:42 2011
> New Revision: 127913
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=127913&view=rev
> Log:
> Match a few more obvious patterns to revsh. rdar://9147637.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>    llvm/trunk/test/CodeGen/ARM/rev.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=127913&r1=127912&r2=127913&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Mar 18 16:52:42 2011
> @@ -2976,10 +2976,18 @@
>                IIC_iUNAr, "revsh", "\t$Rd, $Rm",
>                [(set GPR:$Rd,
>                   (sext_inreg
> -                    (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
> +                    (or (srl GPR:$Rm, (i32 8)),
>                         (shl GPR:$Rm, (i32 8))), i16))]>,
>                Requires<[IsARM, HasV6]>;
> 
> +def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
> +                               (shl GPR:$Rm, (i32 8))), i16),
> +               (REVSH GPR:$Rm)>;
> +
> +// Need the AddedComplexity or else MOVs + REV would be chosen.
> +let AddedComplexity = 5 in
> +def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
> +
> def lsl_shift_imm : SDNodeXForm<imm, [{
>   unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
>   return CurDAG->getTargetConstant(Sh, MVT::i32);
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=127913&r1=127912&r2=127913&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Mar 18 16:52:42 2011
> @@ -2579,9 +2579,15 @@
>                        "revsh", ".w\t$Rd, $Rm",
>                  [(set rGPR:$Rd,
>                     (sext_inreg
> -                      (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
> +                      (or (srl rGPR:$Rm, (i32 8)),
>                           (shl rGPR:$Rm, (i32 8))), i16))]>;
> 
> +def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
> +                            (shl rGPR:$Rm, (i32 8))), i16),
> +            (t2REVSH rGPR:$Rm)>;
> +
> +def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
> +
> def t2PKHBT : T2ThreeReg<
>             (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
>                   IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
> 
> Modified: llvm/trunk/test/CodeGen/ARM/rev.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/rev.ll?rev=127913&r1=127912&r2=127913&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/rev.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/rev.ll Fri Mar 18 16:52:42 2011
> @@ -1,6 +1,6 @@
> ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s
> 
> -define i32 @test1(i32 %X) {
> +define i32 @test1(i32 %X) nounwind {
> ; CHECK: test1
> ; CHECK: rev16 r0, r0
>         %tmp1 = lshr i32 %X, 8
> @@ -16,7 +16,7 @@
>         ret i32 %tmp14
> }
> 
> -define i32 @test2(i32 %X) {
> +define i32 @test2(i32 %X) nounwind {
> ; CHECK: test2
> ; CHECK: revsh r0, r0
>         %tmp1 = lshr i32 %X, 8
> @@ -28,3 +28,29 @@
>         %tmp5.upgrd.2 = sext i16 %tmp5 to i32
>         ret i32 %tmp5.upgrd.2
> }
> +
> +; rdar://9147637
> +define i32 @test3(i16 zeroext %a) nounwind {
> +entry:
> +; CHECK: test3:
> +; CHECK: revsh r0, r0
> +  %0 = tail call i16 @llvm.bswap.i16(i16 %a)
> +  %1 = sext i16 %0 to i32
> +  ret i32 %1
> +}
> +
> +declare i16 @llvm.bswap.i16(i16) nounwind readnone
> +
> +define i32 @test4(i16 zeroext %a) nounwind {
> +entry:
> +; CHECK: test4:
> +; CHECK: revsh r0, r0
> +  %conv = zext i16 %a to i32
> +  %shr9 = lshr i16 %a, 8
> +  %conv2 = zext i16 %shr9 to i32
> +  %shl = shl nuw nsw i32 %conv, 8
> +  %or = or i32 %conv2, %shl
> +  %sext = shl i32 %or, 16
> +  %conv8 = ashr exact i32 %sext, 16
> +  ret i32 %conv8
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits