[llvm-commits] [llvm] r127680 - in /llvm/trunk: lib/Target/XCore/XCoreRegisterInfo.cpp lib/Target/XCore/XCoreRegisterInfo.h test/CodeGen/XCore/scavenging.ll

Richard Osborne richard at xmos.com
Tue Mar 15 08:10:11 PDT 2011


Author: friedgold
Date: Tue Mar 15 10:10:11 2011
New Revision: 127680

URL: http://llvm.org/viewvc/llvm-project?rev=127680&view=rev
Log:
On the XCore the scavenging slot should be closest to the SP.

Added:
    llvm/trunk/test/CodeGen/XCore/scavenging.ll
Modified:
    llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
    llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h

Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=127680&r1=127679&r2=127680&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Tue Mar 15 10:10:11 2011
@@ -104,6 +104,11 @@
   return TFI->hasFP(MF);
 }
 
+bool
+XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
+  return false;
+}
+
 // This function eliminates ADJCALLSTACKDOWN,
 // ADJCALLSTACKUP pseudo instructions
 void XCoreRegisterInfo::

Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=127680&r1=127679&r2=127680&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Tue Mar 15 10:10:11 2011
@@ -48,6 +48,8 @@
   
   bool requiresRegisterScavenging(const MachineFunction &MF) const;
 
+  bool useFPForScavengingIndex(const MachineFunction &MF) const;
+
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const;

Added: llvm/trunk/test/CodeGen/XCore/scavenging.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/scavenging.ll?rev=127680&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/scavenging.ll (added)
+++ llvm/trunk/test/CodeGen/XCore/scavenging.ll Tue Mar 15 10:10:11 2011
@@ -0,0 +1,52 @@
+; RUN: llc < %s -march=xcore
+ at size = global i32 0		; <i32*> [#uses=1]
+ at g0 = external global i32		; <i32*> [#uses=2]
+ at g1 = external global i32		; <i32*> [#uses=2]
+ at g2 = external global i32		; <i32*> [#uses=2]
+ at g3 = external global i32		; <i32*> [#uses=2]
+ at g4 = external global i32		; <i32*> [#uses=2]
+ at g5 = external global i32		; <i32*> [#uses=2]
+ at g6 = external global i32		; <i32*> [#uses=2]
+ at g7 = external global i32		; <i32*> [#uses=2]
+ at g8 = external global i32		; <i32*> [#uses=2]
+ at g9 = external global i32		; <i32*> [#uses=2]
+ at g10 = external global i32		; <i32*> [#uses=2]
+ at g11 = external global i32		; <i32*> [#uses=2]
+
+define void @f() nounwind {
+entry:
+	%x = alloca [100 x i32], align 4		; <[100 x i32]*> [#uses=2]
+	%0 = load i32* @size, align 4		; <i32> [#uses=1]
+	%1 = alloca i32, i32 %0, align 4		; <i32*> [#uses=1]
+	%2 = volatile load i32* @g0, align 4		; <i32> [#uses=1]
+	%3 = volatile load i32* @g1, align 4		; <i32> [#uses=1]
+	%4 = volatile load i32* @g2, align 4		; <i32> [#uses=1]
+	%5 = volatile load i32* @g3, align 4		; <i32> [#uses=1]
+	%6 = volatile load i32* @g4, align 4		; <i32> [#uses=1]
+	%7 = volatile load i32* @g5, align 4		; <i32> [#uses=1]
+	%8 = volatile load i32* @g6, align 4		; <i32> [#uses=1]
+	%9 = volatile load i32* @g7, align 4		; <i32> [#uses=1]
+	%10 = volatile load i32* @g8, align 4		; <i32> [#uses=1]
+	%11 = volatile load i32* @g9, align 4		; <i32> [#uses=1]
+	%12 = volatile load i32* @g10, align 4		; <i32> [#uses=1]
+	%13 = volatile load i32* @g11, align 4		; <i32> [#uses=2]
+	%14 = getelementptr [100 x i32]* %x, i32 0, i32 50		; <i32*> [#uses=1]
+	store i32 %13, i32* %14, align 4
+	volatile store i32 %13, i32* @g11, align 4
+	volatile store i32 %12, i32* @g10, align 4
+	volatile store i32 %11, i32* @g9, align 4
+	volatile store i32 %10, i32* @g8, align 4
+	volatile store i32 %9, i32* @g7, align 4
+	volatile store i32 %8, i32* @g6, align 4
+	volatile store i32 %7, i32* @g5, align 4
+	volatile store i32 %6, i32* @g4, align 4
+	volatile store i32 %5, i32* @g3, align 4
+	volatile store i32 %4, i32* @g2, align 4
+	volatile store i32 %3, i32* @g1, align 4
+	volatile store i32 %2, i32* @g0, align 4
+	%x1 = getelementptr [100 x i32]* %x, i32 0, i32 0		; <i32*> [#uses=1]
+	call void @g(i32* %x1, i32* %1) nounwind
+	ret void
+}
+
+declare void @g(i32*, i32*)





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