[llvm-commits] A patch to add vector-zext support to LLVM

[Duncan Sands]

Hi Nadav,

> +define<4 x i16> @func_1_16() {
> +  %F = load <4 x i1>* undef
> +  %G = zext <4 x i1> %F to <4 x i16>
> +  %H = load <4 x i1>* undef
> +  %Y = zext <4 x i1> %H to <4 x i16>
> +  %T = sub <4 x i16> %Y, %G
> +  store <4 x i16>%T , <4 x i16>* undef
> +  ret <4 x i16> %T
> +}

this and the other i1 tests are dubious since codegen is known not to
support vectors of i1.

> Property changes on: test/CodeGen/X86/vec_zext.ll
> ___________________________________________________________________
> Added: svn:eol-style
>    + native

What's with the property change?

> --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp	(revision 125764)
> +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp	(working copy)
> @@ -3887,7 +3887,9 @@
>    }
>
>    // fold (zext (load x)) -> (zext (truncate (zextload x)))
> -  if (ISD::isNON_EXTLoad(N0.getNode()) &&
> +  // none of the supporded targets knows how to perform load  and vector_zext

none -> None
supporded -> supported
There are two spaces between "load" and "and vector_zext", should be one.

> +  // in one instruction. We only perform this transformation on scalar zext.

There should be two spaces after a full stop.

Otherwise it looks good to me.

Ciao, Duncan.