[llvm-commits] [llvm] r125465 - in /llvm/trunk: include/llvm/CodeGen/ISDOpcodes.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

[Duncan Sands]

Hi Chris,

> +    /// Shift and rotation operations.  After legalization, the type of the
> +    /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
> +    /// the shift amount can be any type, but care must be taken to ensure it is
> +    /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
> +    /// legalization, types like i1024 can occur and i8 doesn't have enough bits
> +    /// to represent the shift amount.  By convention, DAGCombine and IRBuilder
> +    /// forces these shift amounts to i32 for simplicity.

IRBuilder -> SelectionDAGBuilder.  Another solution is to use the type of the
first operand for the type of the shift amount (like is done in the IR).  That
would get rid of inelegant logic like the following:

> +    // Ensure that the shift amount is wide enough for the shifted value.
> +    if (VT.getSizeInBits()>= 256)
> +      ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);

Ciao, Duncan.