[llvm-commits] [llvm] r124443 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Andrew Trick]

Author: atrick
Date: Thu Jan 27 15:28:51 2011
New Revision: 124443

URL: http://llvm.org/viewvc/llvm-project?rev=124443&view=rev
Log:
Remove a temporary workaround for a lencod miscompile. Depends on the fix in r124442.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=124443&r1=124442&r2=124443&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jan 27 15:28:51 2011
@@ -1645,13 +1645,11 @@
     // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
     // counts data deps.  To be more precise, we could maintain a
     // NumDataSuccsLeft count.
-    /* FIXME: exposing a downstream bug, JM/lencode miscompile
     if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
       DEBUG(dbgs() << "  SU(" << PredSU->NodeNum << ") live across SU("
             << SU->NodeNum << ")\n");
       continue;
     }
-    */
     const SDNode *PN = PredSU->getNode();
     if (!PN->isMachineOpcode()) {
       if (PN->getOpcode() == ISD::CopyFromReg) {