[llvm-commits] [llvm] r124191 - /llvm/trunk/include/llvm/Target/TargetSelectionDAG.td

[David Greene]

Author: greened
Date: Tue Jan 25 10:16:32 2011
New Revision: 124191

URL: http://llvm.org/viewvc/llvm-project?rev=124191&view=rev
Log:

[AVX] Add TableGen classes for vector/subvector type constraints.
This will be used to check patterns referencing a forthcoming
INSERT_SUBVECTOR SDNode and will also be used to check
EXTRACT_SUBVECTOR nodes.

Modified:
    llvm/trunk/include/llvm/Target/TargetSelectionDAG.td

Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=124191&r1=124190&r2=124191&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue Jan 25 10:16:32 2011
@@ -61,6 +61,13 @@
   int OtherOpNum = OtherOp;
 }
 
+/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
+/// with length less that of OtherOp, which is a vector type.
+class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
+  : SDTypeConstraint<ThisOp> {
+  int OtherOpNum = OtherOp;
+}
+
 //===----------------------------------------------------------------------===//
 // Selection DAG Type Profile definitions.
 //
@@ -183,6 +190,13 @@
   SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
 ]>;
 
+def SDTSubVecExtract : SDTypeProfile<1, 1, [// subvector extract
+  SDTCisSubVecOfVec<0,1>
+]>;
+def SDTSubVecInsert : SDTypeProfile<1, 2, [ // subvector insert
+  SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>
+]>;
+
 def SDTPrefetch : SDTypeProfile<0, 3, [     // prefetch
   SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
 ]>;