[llvm-commits] [llvm] r124137 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Andrew Trick]

Author: atrick
Date: Mon Jan 24 13:08:15 2011
New Revision: 124137

URL: http://llvm.org/viewvc/llvm-project?rev=124137&view=rev
Log:
Temporarily workaround JM/lencod miscompile (SIGSEGV).
rdar://problem/8893967

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=124137&r1=124136&r2=124137&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jan 24 13:08:15 2011
@@ -1645,11 +1645,13 @@
     // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
     // counts data deps.  To be more precise, we could maintain a
     // NumDataSuccsLeft count.
+    /* FIXME: exposing a downstream bug, JM/lencode miscompile
     if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
       DEBUG(dbgs() << "  SU(" << PredSU->NodeNum << ") live across SU("
             << SU->NodeNum << ")\n");
       continue;
     }
+    */
     const SDNode *PN = PredSU->getNode();
     if (!PN->isMachineOpcode()) {
       if (PN->getOpcode() == ISD::CopyFromReg) {