[llvm-commits] [llvm] r123722 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/thumb2_instructions.s

[Daniel Dunbar]

Author: ddunbar
Date: Mon Jan 17 21:06:03 2011
New Revision: 123722

URL: http://llvm.org/viewvc/llvm-project?rev=123722&view=rev
Log:
McARM: Start marking T2 address operands as such, for the benefit of the parser.

Added:
    llvm/trunk/test/MC/ARM/thumb2_instructions.s
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=123722&r1=123721&r2=123722&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jan 17 21:06:03 2011
@@ -129,6 +129,7 @@
   let PrintMethod = "printAddrModeImm12Operand";
   let EncoderMethod = "getAddrModeImm12OpValue";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemMode5AsmOperand;
 }
 
 // ADR instruction labels.
@@ -143,6 +144,7 @@
   let PrintMethod = "printT2AddrModeImm8Operand";
   let EncoderMethod = "getT2AddrModeImm8OpValue";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemMode5AsmOperand;
 }
 
 def t2am_imm8_offset : Operand<i32>,
@@ -150,6 +152,7 @@
                                       [], [SDNPWantRoot]> {
   let PrintMethod = "printT2AddrModeImm8OffsetOperand";
   let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
+  let ParserMatchClass = MemMode5AsmOperand;
 }
 
 // t2addrmode_imm8s4  := reg +/- (imm8 << 2)
@@ -157,6 +160,7 @@
   let PrintMethod = "printT2AddrModeImm8s4Operand";
   let EncoderMethod = "getT2AddrModeImm8s4OpValue";
   let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
+  let ParserMatchClass = MemMode5AsmOperand;
 }
 
 def t2am_imm8s4_offset : Operand<i32> {
@@ -169,6 +173,7 @@
   let PrintMethod = "printT2AddrModeSoRegOperand";
   let EncoderMethod = "getT2AddrModeSORegOpValue";
   let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
+  let ParserMatchClass = MemMode5AsmOperand;
 }
 
 

Added: llvm/trunk/test/MC/ARM/thumb2_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2_instructions.s?rev=123722&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2_instructions.s (added)
+++ llvm/trunk/test/MC/ARM/thumb2_instructions.s Mon Jan 17 21:06:03 2011
@@ -0,0 +1,12 @@
+@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t
+@ RUN: FileCheck < %t %s
+
+	.syntax unified
+	.text
+
+@ FIXME: This is not the correct instruction representation, but at least we are
+@ parsing the ldr to something.
+@
+@ CHECK: ldr r0, [r7, #258]
+	ldr	r0, [r7, #-8]
+