[llvm-commits] [llvm] r122370 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Andrew Trick]

Author: atrick
Date: Tue Dec 21 16:27:44 2010
New Revision: 122370

URL: http://llvm.org/viewvc/llvm-project?rev=122370&view=rev
Log:
In DelayForLiveRegsBottomUp, handle instructions that read and write
the same physical register. Simplifies the fix from the previous
checkin r122211.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=122370&r1=122369&r2=122370&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Dec 21 16:27:44 2010
@@ -660,9 +660,12 @@
 
   SmallSet<unsigned, 4> RegAdded;
   // If this node would clobber any "live" register, then it's not ready.
+  //
+  // If SU is the currently live definition of the same register that it uses,
+  // then we are free to schedule it.
   for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
        I != E; ++I) {
-    if (I->isAssignedRegDep())
+    if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
       CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
                          RegAdded, LRegs, TRI);
   }
@@ -703,20 +706,6 @@
       CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
   }
 
-
-  // Okay, we now know all of the live registers that are defined by an
-  // immediate predecessor.  It is ok to kill these registers if we are also
-  // using it.
-  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I) {
-    if (I->isAssignedRegDep() &&
-        LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
-      unsigned Reg = I->getReg();
-      if (RegAdded.erase(Reg))
-        LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg));
-    }
-  }
-
   return !LRegs.empty();
 }