[llvm-commits] [llvm] r121584 - in /llvm/trunk/lib/CodeGen: AllocationOrder.cpp RegAllocGreedy.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Dec 10 16:21:05 2010
New Revision: 121584

URL: http://llvm.org/viewvc/llvm-project?rev=121584&view=rev
Log:
Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.

Modified:
    llvm/trunk/lib/CodeGen/AllocationOrder.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.cpp?rev=121584&r1=121583&r2=121584&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AllocationOrder.cpp (original)
+++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp Fri Dec 10 16:21:05 2010
@@ -36,6 +36,10 @@
   if (Hint && TargetRegisterInfo::isVirtualRegister(Hint))
     Hint = VRM.getPhys(Hint);
 
+  // The remaining allocation order may depend on the hint.
+  tie(Begin, End) = VRM.getTargetRegInfo()
+        .getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
+
   // Target-dependent hints require resolution.
   if (HintPair.first)
     Hint = VRM.getTargetRegInfo().ResolveRegAllocHint(HintPair.first, Hint,
@@ -45,10 +49,6 @@
   if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
                !RC->contains(Hint) || ReservedRegs.test(Hint)))
     Hint = 0;
-
-  // The remaining allocation order may also depend on the hint.
-  tie(Begin, End) = VRM.getTargetRegInfo()
-        .getAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction());
 }
 
 unsigned AllocationOrder::next() {

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121584&r1=121583&r2=121584&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Dec 10 16:21:05 2010
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "regalloc"
+#include "AllocationOrder.h"
 #include "LiveIntervalUnion.h"
 #include "RegAllocBase.h"
 #include "Spiller.h"
@@ -175,12 +176,9 @@
   assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
          "inconsistent phys reg assigment");
 
-  const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg);
-  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
-         E = TRC->allocation_order_end(*MF);
-       I != E; ++I) {
-    unsigned PhysReg = *I;
-    if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
+  AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
+  while (unsigned PhysReg = Order.next()) {
+    if (PhysReg == OldPhysReg)
       continue;
 
     if (checkUncachedInterference(InterferingVReg, PhysReg))
@@ -235,21 +233,8 @@
   const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
   DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
 
-  // Preferred physical register computed from hints.
-  unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
-
-  // Try a hinted allocation.
-  if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
-      checkPhysRegInterference(VirtReg, Hint) == 0)
-    return Hint;
-
-  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
-         E = TRC->allocation_order_end(*MF);
-       I != E; ++I) {
-
-    unsigned PhysReg = *I;
-    if (ReservedRegs.test(PhysReg)) continue;
-
+  AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
+  while (unsigned PhysReg = Order.next()) {
     // Check interference and as a side effect, intialize queries for this
     // VirtReg and its aliases.
     unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);