[llvm-commits] [llvm] r121414 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMMCCodeEmitter.cpp

[Owen Anderson]

Author: resistor
Date: Thu Dec  9 15:34:47 2010
New Revision: 121414

URL: http://llvm.org/viewvc/llvm-project?rev=121414&view=rev
Log:
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches.  This is still not perfect,
but it gets many more of them correct than it did previously.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121414&r1=121413&r2=121414&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec  9 15:34:47 2010
@@ -101,6 +101,7 @@
   case ARM::fixup_arm_ldst_pcrel_12:
     // ARM PC-relative values are offset by 8.
     Value -= 4;
+    // FALLTHROUGH
   case ARM::fixup_t2_ldst_pcrel_12: {
     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     Value -= 4;
@@ -140,7 +141,7 @@
     // Offset by 8 just as above.
     return 0xffffff & ((Value - 8) >> 2);
   case ARM::fixup_t2_branch: {
-    Value = Value - 8;
+    Value = Value - 6;
     Value >>= 1; // Low bit is not encoded.
     
     uint64_t out = 0;

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121414&r1=121413&r2=121414&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Dec  9 15:34:47 2010
@@ -53,7 +53,8 @@
       { "fixup_t2_pcrel_10",        0,    32,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_adr_pcrel_12",   1,    24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_branch",         1,    24,   MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_t2_branch",          0,    32,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_t2_branch",          0,    32,   MCFixupKindInfo::FKF_IsPCRel |
+                                                MCFixupKindInfo::FKF_IsAligned},
       { "fixup_arm_thumb_bl",       0,    32,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_thumb_blx",      0,    32,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_thumb_cb",       0,    16,   MCFixupKindInfo::FKF_IsPCRel },