[llvm-commits] [llvm] r121020 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

[Jim Grosbach]

Author: grosbach
Date: Mon Dec  6 12:30:57 2010
New Revision: 121020

URL: http://llvm.org/viewvc/llvm-project?rev=121020&view=rev
Log:
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
the instruction is predicated, reg0 otherwise.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=121020&r1=121019&r2=121020&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Dec  6 12:30:57 2010
@@ -263,8 +263,8 @@
   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
-    // FIXME: What belongs here?
-    Inst.addOperand(MCOperand::CreateReg(0));
+    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
+    Inst.addOperand(MCOperand::CreateReg(RegNum));
   }
 
   void addCCOutOperands(MCInst &Inst, unsigned N) const {