[llvm-commits] [llvm] r120849 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

[Jim Grosbach]

On Dec 3, 2010, at 2:58 PM, Bill Wendling wrote:

> On Dec 3, 2010, at 2:33 PM, Jim Grosbach wrote:
> 
>> Author: grosbach
>> Date: Fri Dec  3 16:33:42 2010
>> New Revision: 120849
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=120849&view=rev
>> Log:
>> Remove incorrect BL target encoding (it's similar to, but not the same as the
>> ARM instruction). Add encoding of bits 13 and 11.
>> 
> Hi Jim,
> 
> Are bits 13 and 11 always supposed to be set? It looks like they're variable in the docs:

They're always set for the Thumb1 version, yes. If we need versions with them not set for T2, we'll want to add new patterns for them*.

It's kinda weird the way they document it. 

ARMv4T, ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1
ARMv6T2, ARMv7 otherwise

-Jim

* Well, more likely add a parameterized canonical instruction pattern and make the T1 and T2 (w/ and w/o r9 clobber) versions pseudos that resolve to it appropriately.


> 
> 	1 1 1 1 0 | S | imm10 || 1 1 | J1 | 1 | J2 | imm11
> 
> I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S);
> imm32 = SignExtend(S:I1:I2:imm10:imm11:’0’, 32);
> toARM = FALSE;
> if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
> 
> So if we go by that, then it looks like we should check the I1 and I2 bits in imm32 and do the following:
> 
> J1 = S EOR NOT(I1)
> J2 = S EOR NOT(I2)
> 
> ?
> 
> -bw
>