[llvm-commits] [llvm] r120584 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMFixupKinds.h ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Dec  1 12:51:32 2010
New Revision: 120584

URL: http://llvm.org/viewvc/llvm-project?rev=120584&view=rev
Log:
10 bits, not 12.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=120584&r1=120583&r2=120584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Dec  1 12:51:32 2010
@@ -64,7 +64,7 @@
       // These values don't encode the low two bits since they're always zero.
       // Offset by 8 just as above.
       return (Value - 8) >> 2;
-    case ARM::fixup_arm_vfp_pcrel_12: {
+    case ARM::fixup_arm_vfp_pcrel_10: {
       // Offset by 8 just as above.
       Value = Value - 8;
       bool isAdd = true;
@@ -202,7 +202,7 @@
   default: llvm_unreachable("Unknown fixup kind!");
   case FK_Data_4: return 4;
   case ARM::fixup_arm_pcrel_12: return 3;
-  case ARM::fixup_arm_vfp_pcrel_12: return 3;
+  case ARM::fixup_arm_vfp_pcrel_10: return 3;
   case ARM::fixup_arm_branch: return 3;
   }
 }

Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=120584&r1=120583&r2=120584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Dec  1 12:51:32 2010
@@ -17,10 +17,10 @@
 enum Fixups {
   // fixup_arm_pcrel_12 - 12-bit PC relative relocation for symbol addresses
   fixup_arm_pcrel_12 = FirstTargetFixupKind,
-  // fixup_arm_vfp_pcrel_12 - 12-bit PC relative relocation for symbol addresses
+  // fixup_arm_vfp_pcrel_10 - 10-bit PC relative relocation for symbol addresses
   // used in VFP instructions where the lower 2 bits are not encoded (so it's
   // encoded as an 8-bit immediate).
-  fixup_arm_vfp_pcrel_12,
+  fixup_arm_vfp_pcrel_10,
   // fixup_arm_brnach - 24-bit PC relative relocation for direct branch
   // instructions.
   fixup_arm_branch,

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=120584&r1=120583&r2=120584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec  1 12:51:32 2010
@@ -47,7 +47,7 @@
     const static MCFixupKindInfo Infos[] = {
       // name                     offset  bits  flags
       { "fixup_arm_pcrel_12",     1,      24,   MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_arm_vfp_pcrel_12", 1,      24,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_arm_vfp_pcrel_10", 1,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_branch",       1,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_movt_hi16",    0,      16,   0 },
       { "fixup_arm_movw_lo16",    0,      16,   0 },
@@ -613,7 +613,7 @@
 
     assert(MO.isExpr() && "Unexpected machine operand type!");
     const MCExpr *Expr = MO.getExpr();
-    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
+    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_10);
     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 
     ++MCNumCPRelocations;