[llvm-commits] [llvm] r120480 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Tue Nov 30 16:40:36 2010
New Revision: 120480

URL: http://llvm.org/viewvc/llvm-project?rev=120480&view=rev
Log:
Fix handling of ARM negative pc-relative fixups for loads and stores.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=120480&r1=120479&r2=120480&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Nov 30 16:40:36 2010
@@ -131,8 +131,8 @@
   switch (Kind) {
   default: llvm_unreachable("Unknown fixup kind!");
   case FK_Data_4: return 4;
-  case ARM::fixup_arm_pcrel_12: return 2;
-  case ARM::fixup_arm_vfp_pcrel_12: return 1;
+  case ARM::fixup_arm_pcrel_12: return 3;
+  case ARM::fixup_arm_vfp_pcrel_12: return 3;
   case ARM::fixup_arm_branch: return 3;
   }
 }
@@ -143,14 +143,36 @@
     llvm_unreachable("Unknown fixup kind!");
   case FK_Data_4:
     return Value;
-  case ARM::fixup_arm_pcrel_12:
+  case ARM::fixup_arm_pcrel_12: {
+    bool isAdd = true;
     // ARM PC-relative values are offset by 8.
-    return Value - 8;
+    Value -= 8;
+    if ((int64_t)Value < 0) {
+      Value = -Value;
+      isAdd = false;
+    }
+    assert ((Value < 4096) && "Out of range pc-relative fixup value!");
+    Value |= isAdd << 23;
+    return Value;
+  }
   case ARM::fixup_arm_branch:
-  case ARM::fixup_arm_vfp_pcrel_12:
     // These values don't encode the low two bits since they're always zero.
     // Offset by 8 just as above.
     return (Value - 8) >> 2;
+  case ARM::fixup_arm_vfp_pcrel_12: {
+    // Offset by 8 just as above.
+    Value = Value - 8;
+    bool isAdd = true;
+    if ((int64_t)Value < 0) {
+      Value = -Value;
+      isAdd = false;
+    }
+    // These values don't encode the low two bits since they're always zero.
+    Value >>= 2;
+    assert ((Value < 256) && "Out of range pc-relative fixup value!");
+    Value |= isAdd << 23;
+    return Value;
+  }
   }
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=120480&r1=120479&r2=120480&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov 30 16:40:36 2010
@@ -46,8 +46,8 @@
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
     const static MCFixupKindInfo Infos[] = {
       // name                     offset  bits  flags
-      { "fixup_arm_pcrel_12",     2,      12,   MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_arm_vfp_pcrel_12", 3,      8,    MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_arm_pcrel_12",     1,      24,   MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_arm_vfp_pcrel_12", 1,      24,   MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_arm_branch",       1,      24,   MCFixupKindInfo::FKF_IsPCRel },
     };
 
@@ -395,6 +395,7 @@
   if (!MO.isReg()) {
     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
     Imm12 = 0;
+    isAdd = false ; // 'U' bit is set as part of the fixup.
 
     assert(MO.isExpr() && "Unexpected machine operand type!");
     const MCExpr *Expr = MO.getExpr();
@@ -574,11 +575,13 @@
   // {8}    = (U)nsigned (add == '1', sub == '0')
   // {7-0}  = imm8
   unsigned Reg, Imm8;
+  bool isAdd;
   // If The first operand isn't a register, we have a label reference.
   const MCOperand &MO = MI.getOperand(OpIdx);
   if (!MO.isReg()) {
     Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
     Imm8 = 0;
+    isAdd = false; // 'U' bit is handled as part of the fixup.
 
     assert(MO.isExpr() && "Unexpected machine operand type!");
     const MCExpr *Expr = MO.getExpr();
@@ -586,12 +589,14 @@
     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 
     ++MCNumCPRelocations;
-  } else
+  } else {
     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
+    isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
+  }
 
   uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
   // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
-  if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
+  if (isAdd)
     Binary |= (1 << 8);
   Binary |= (Reg << 9);
   return Binary;