[llvm-commits] [llvm] r120306 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

[Owen Anderson]

Author: resistor
Date: Mon Nov 29 12:54:38 2010
New Revision: 120306

URL: http://llvm.org/viewvc/llvm-project?rev=120306&view=rev
Log:
Thumb2 encodings for branches and IT blocks.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=120306&r1=120305&r2=120306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Nov 29 12:54:38 2010
@@ -2921,6 +2921,13 @@
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 1;
+
+  bits<20> target;
+  let Inst{26} = target{19};
+  let Inst{11} = target{18};
+  let Inst{13} = target{17};
+  let Inst{21-16} = target{16-11};
+  let Inst{10-0} = target{10-0};
 }
 
 let isNotDuplicable = 1, isIndirectBranch = 1,
@@ -3004,6 +3011,11 @@
   // 16-bit instruction.
   let Inst{31-16} = 0x0000;
   let Inst{15-8} = 0b10111111;
+
+  bits<4> cc;
+  bits<4> mask;
+  let Inst{7-4} = cc{3-0};
+  let Inst{3-0} = mask{3-0};
 }
 
 // Branch and Exchange Jazelle -- for disassembly only
@@ -3015,6 +3027,9 @@
   let Inst{25-20} = 0b111100;
   let Inst{15-14} = 0b10;
   let Inst{12} = 0;
+  
+  bits<4> func;
+  let Inst{19-16} = func{3-0};
 }
 
 // Change Processor State is a system instruction -- for disassembly only.