[llvm-commits] [llvm] r120286 - in /llvm/trunk: lib/Target/CellSPU/SPUSubtarget.cpp lib/Target/CellSPU/SPUSubtarget.h test/CodeGen/CellSPU/sext128.ll test/CodeGen/CellSPU/shuffles.ll

[Kalle Raiskila]

Author: kraiskil
Date: Mon Nov 29 04:30:25 2010
New Revision: 120286

URL: http://llvm.org/viewvc/llvm-project?rev=120286&view=rev
Log:
Enable PostRA scheduling for SPU. 
This speeds up selected test cases with up to
5% - no slowdowns observed.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
    llvm/trunk/test/CodeGen/CellSPU/sext128.ll
    llvm/trunk/test/CodeGen/CellSPU/shuffles.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=120286&r1=120285&r2=120286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Mon Nov 29 04:30:25 2010
@@ -14,6 +14,8 @@
 #include "SPUSubtarget.h"
 #include "SPU.h"
 #include "SPUGenSubtarget.inc"
+#include "llvm/ADT/SmallVector.h"
+#include "SPURegisterInfo.h"
 
 using namespace llvm;
 
@@ -34,3 +36,22 @@
 /// producing code for the JIT.
 void SPUSubtarget::SetJITMode() {
 }
+
+/// Enable PostRA scheduling for optimization levels -O2 and -O3.
+bool SPUSubtarget::enablePostRAScheduler(
+                       CodeGenOpt::Level OptLevel,
+                       TargetSubtarget::AntiDepBreakMode& Mode,
+                       RegClassVector& CriticalPathRCs) const {
+  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+  // CriticalPathsRCs seems to be the set of
+  // RegisterClasses that antidep breakings are performed for.
+  // Do it for all register classes 
+  CriticalPathRCs.clear();
+  CriticalPathRCs.push_back(&SPU::R8CRegClass);
+  CriticalPathRCs.push_back(&SPU::R16CRegClass);
+  CriticalPathRCs.push_back(&SPU::R32CRegClass);
+  CriticalPathRCs.push_back(&SPU::R32FPRegClass);
+  CriticalPathRCs.push_back(&SPU::R64CRegClass);
+  CriticalPathRCs.push_back(&SPU::VECREGRegClass);
+  return OptLevel >= CodeGenOpt::Default;
+}

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=120286&r1=120285&r2=120286&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Mon Nov 29 04:30:25 2010
@@ -84,6 +84,10 @@
              "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128"
              "-s:128:128-n32:64";
     }
+
+    bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
+                               TargetSubtarget::AntiDepBreakMode& Mode,
+                               RegClassVector& CriticalPathRCs) const;
   };
 } // End llvm namespace
 

Modified: llvm/trunk/test/CodeGen/CellSPU/sext128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/sext128.ll?rev=120286&r1=120285&r2=120286&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/sext128.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/sext128.ll Mon Nov 29 04:30:25 2010
@@ -13,8 +13,8 @@
 ; CHECK:	long	66051
 ; CHECK: 	long	67438087
 ; CHECK-NOT: rotqmbyi
-; CHECK: 	rotmai
 ; CHECK:	lqa
+; CHECK: 	rotmai
 ; CHECK:	shufb
 }
 
@@ -27,8 +27,8 @@
 ; CHECK: 	long	269488144
 ; CHECK:	long	66051
 ; CHECK-NOT: rotqmbyi
-; CHECK: 	rotmai
 ; CHECK:	lqa
+; CHECK: 	rotmai
 ; CHECK:	shufb
 }
 
@@ -42,8 +42,8 @@
 ; CHECK: 	long	269488144
 ; CHECK:	long	66051
 ; CHECK-NOT: rotqmbyi
-; CHECK: 	rotmai
 ; CHECK:	lqa
+; CHECK: 	rotmai
 ; CHECK:	shufb
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/shuffles.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shuffles.ll?rev=120286&r1=120285&r2=120286&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/shuffles.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/shuffles.ll Mon Nov 29 04:30:25 2010
@@ -1,4 +1,4 @@
-; RUN: llc --march=cellspu < %s | FileCheck %s
+; RUN: llc -O1  --march=cellspu < %s | FileCheck %s
 
 define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) {
   ; CHECK: cwd {{\$.}}, 0($sp)