[llvm-commits] [llvm] r119713 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

[Jim Grosbach]

Author: grosbach
Date: Thu Nov 18 12:01:40 2010
New Revision: 119713

URL: http://llvm.org/viewvc/llvm-project?rev=119713&view=rev
Log:
ARMPseudoInst instructions should default to being considered a single 4-byte
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=119713&r1=119712&r2=119713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Nov 18 12:01:40 2010
@@ -249,6 +249,9 @@
 class ARMPseudoInst<dag oops, dag iops, InstrItinClass itin,
                     list<dag> pattern>
   : PseudoInst<oops, iops, itin, pattern> {
+  // Default these to 4byte size, as they're almost always expanded to a
+  // single instruction. Any exceptions can override the SZ field value.
+  let SZ = Size4Bytes;
   list<Predicate> Predicates = [IsARM];
 }