[llvm-commits] [llvm] r118997 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td InstPrinter/ARMInstPrinter.cpp

[Bill Wendling]

Author: void
Date: Sat Nov 13 04:40:19 2010
New Revision: 118997

URL: http://llvm.org/viewvc/llvm-project?rev=118997&view=rev
Log:
Minor cleanups:

- Get the opcode once.
- Add a ParserMatchClass to reglist.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118997&r1=118996&r2=118997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Nov 13 04:40:19 2010
@@ -285,16 +285,17 @@
 }
 
 // A list of registers separated by comma. Used by load/store multiple.
-def reglist : Operand<i32> {
-  string EncoderMethod = "getRegisterListOpValue";
-  let PrintMethod = "printRegisterList";
-}
-
 def RegListAsmOperand : AsmOperandClass {
   let Name = "RegList";
   let SuperClasses = [];
 }
 
+def reglist : Operand<i32> {
+  string EncoderMethod = "getRegisterListOpValue";
+  let ParserMatchClass = RegListAsmOperand;
+  let PrintMethod = "printRegisterList";
+}
+
 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
 def cpinst_operand : Operand<i32> {
   let PrintMethod = "printCPInstOperand";

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=118997&r1=118996&r2=118997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Sat Nov 13 04:40:19 2010
@@ -31,8 +31,10 @@
 
 
 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+  unsigned Opcode = MI->getOpcode();
+
   // Check for MOVs and print canonical forms, instead.
-  if (MI->getOpcode() == ARM::MOVs) {
+  if (Opcode == ARM::MOVs) {
     // FIXME: Thumb variants?
     const MCOperand &Dst = MI->getOperand(0);
     const MCOperand &MO1 = MI->getOperand(1);
@@ -61,7 +63,7 @@
   }
 
   // A8.6.123 PUSH
-  if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
+  if ((Opcode == ARM::STM_UPD || Opcode == ARM::t2STM_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@@ -74,7 +76,7 @@
   }
 
   // A8.6.122 POP
-  if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
+  if ((Opcode == ARM::LDM_UPD || Opcode == ARM::t2LDM_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@@ -87,7 +89,7 @@
   }
 
   // A8.6.355 VPUSH
-  if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
+  if ((Opcode == ARM::VSTMS_UPD || Opcode == ARM::VSTMD_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@@ -100,7 +102,7 @@
   }
 
   // A8.6.354 VPOP
-  if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
+  if ((Opcode == ARM::VLDMS_UPD || Opcode == ARM::VLDMD_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@@ -113,7 +115,7 @@
   }
 
   printInstruction(MI, O);
- }
+}
 
 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                   raw_ostream &O) {