[llvm-commits] [llvm] r118801 - in /llvm/trunk/lib/Target/ARM: ARMAsmBackend.cpp ARMCodeEmitter.cpp ARMFixupKinds.h ARMInstrInfo.td ARMMCCodeEmitter.cpp
Jim Grosbach
grosbach at apple.com
Thu Nov 11 10:04:49 PST 2010
Author: grosbach
Date: Thu Nov 11 12:04:49 2010
New Revision: 118801
URL: http://llvm.org/viewvc/llvm-project?rev=118801&view=rev
Log:
Encoding of destination fixup for ARM branch and conditional branch
instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=118801&r1=118800&r2=118801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Nov 11 12:04:49 2010
@@ -138,12 +138,13 @@
}
};
-static unsigned getFixupKindLog2Size(unsigned Kind) {
+static unsigned getFixupKindNumBytes(unsigned Kind) {
switch (Kind) {
default: llvm_unreachable("Unknown fixup kind!");
- case FK_Data_4: return 2;
+ case FK_Data_4: return 4;
case ARM::fixup_arm_pcrel_12: return 2;
case ARM::fixup_arm_vfp_pcrel_12: return 1;
+ case ARM::fixup_arm_branch: return 3;
}
}
@@ -156,16 +157,17 @@
case ARM::fixup_arm_pcrel_12:
// ARM PC-relative values are offset by 8.
return Value - 8;
+ case ARM::fixup_arm_branch:
case ARM::fixup_arm_vfp_pcrel_12:
- // The VFP ld/st immediate value doesn't encode the low two bits since
- // they're always zero. Offset by 8 just as above.
+ // These values don't encode the low two bits since they're always zero.
+ // Offset by 8 just as above.
return (Value - 8) >> 2;
}
}
void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
- uint64_t Value) const {
- unsigned NumBytes = getFixupKindLog2Size(Fixup.getKind());
+ uint64_t Value) const {
+ unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
Value = adjustFixupValue(Fixup.getKind(), Value);
assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=118801&r1=118800&r2=118801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 11 12:04:49 2010
@@ -161,6 +161,8 @@
// are already handled elsewhere. They are placeholders to allow this
// encoder to continue to function until the MC encoder is sufficiently
// far along that this one can be eliminated entirely.
+ unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
+ const { return 0; }
unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=118801&r1=118800&r2=118801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Thu Nov 11 12:04:49 2010
@@ -20,7 +20,14 @@
// fixup_arm_vfp_pcrel_12 - 12-bit PC relative relocation for symbol addresses
// used in VFP instructions where the lower 2 bits are not encoded (so it's
// encoded as an 8-bit immediate).
- fixup_arm_vfp_pcrel_12
+ fixup_arm_vfp_pcrel_12,
+ // fixup_arm_brnach - 24-bit PC relative relocation for direct branch
+ // instructions.
+ fixup_arm_branch,
+
+ // Marker
+ LastTargetFixupKind,
+ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
};
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118801&r1=118800&r2=118801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 11 12:04:49 2010
@@ -274,7 +274,9 @@
//
// Branch target.
-def brtarget : Operand<OtherVT>;
+def brtarget : Operand<OtherVT> {
+ string EncoderMethod = "getBranchTargetOpValue";
+}
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
@@ -1363,7 +1365,10 @@
let isBarrier = 1 in {
let isPredicable = 1 in
def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
- "b\t$target", [(br bb:$target)]>;
+ "b\t$target", [(br bb:$target)]> {
+ bits<24> target;
+ let Inst{23-0} = target;
+ }
let isNotDuplicable = 1, isIndirectBranch = 1,
// FIXME: $imm field is not specified by asm string. Mark as cgonly.
@@ -1406,7 +1411,10 @@
// a two-value operand where a dag node expects two operands. :(
def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
IIC_Br, "b", "\t$target",
- [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
+ [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
+ bits<24> target;
+ let Inst{23-0} = target;
+ }
}
// Branch and Exchange Jazelle -- for disassembly only
Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118801&r1=118800&r2=118801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 11 12:04:49 2010
@@ -41,12 +41,14 @@
~ARMMCCodeEmitter() {}
- unsigned getNumFixupKinds() const { return 2; }
+ unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[] = {
- { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
+ // name offset bits flags
+ { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
};
if (Kind < FirstTargetFixupKind)
@@ -72,6 +74,11 @@
unsigned &Reg, unsigned &Imm,
SmallVectorImpl<MCFixup> &Fixups) const;
+ /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
+ /// branch target.
+ uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
/// operand.
uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
@@ -247,6 +254,24 @@
return isAdd;
}
+/// getBranchTargetOpValue - Return encoding info for 24-bit immediate
+/// branch target.
+uint32_t ARMMCCodeEmitter::
+getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups) const {
+ const MCOperand &MO = MI.getOperand(OpIdx);
+
+ // If the destination is an immediate, we have nothing to do.
+ if (MO.isImm()) return MO.getImm();
+ assert (MO.isExpr() && "Unexpected branch target type!");
+ const MCExpr *Expr = MO.getExpr();
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
+ Fixups.push_back(MCFixup::Create(0, Expr, Kind));
+
+ // All of the information is in the fixup.
+ return 0;
+}
+
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
uint32_t ARMMCCodeEmitter::
getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
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