[llvm-commits] [llvm] r118587 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Tue Nov  9 11:38:15 2010
New Revision: 118587

URL: http://llvm.org/viewvc/llvm-project?rev=118587&view=rev
Log:
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118587&r1=118586&r2=118587&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Nov  9 11:38:15 2010
@@ -277,6 +277,9 @@
   // ROR - 11
   switch (ShOp) {
   default: llvm_unreachable("Unknown shift opc!");
+  case ARM_AM::no_shift:
+    assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
+    // fall through
   case ARM_AM::lsl: SBits = 0x0; break;
   case ARM_AM::lsr: SBits = 0x1; break;
   case ARM_AM::asr: SBits = 0x2; break;