[llvm-commits] [llvm] r118458 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Bill Wendling]

Author: void
Date: Mon Nov  8 17:51:20 2010
New Revision: 118458

URL: http://llvm.org/viewvc/llvm-project?rev=118458&view=rev
Log:
Get the register and count from the register list operands.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118458&r1=118457&r2=118458&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov  8 17:51:20 2010
@@ -378,14 +378,11 @@
 
 unsigned ARMMCCodeEmitter::
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
-                       SmallVectorImpl<MCFixup> &Fixups) const {
-  // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
-  // register in the list, set the corresponding bit.
-  unsigned Binary = 0;
-  for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
-    unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
-    Binary |= 1 << regno;
-  }
+                       SmallVectorImpl<MCFixup> &) const {
+  // {12-8} = Rd
+  // {7-0}  = count
+  unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
+  Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
   return Binary;
 }