[llvm-commits] [llvm] r118126 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Eric Christopher]

Author: echristo
Date: Tue Nov  2 18:59:09 2010
New Revision: 118126

URL: http://llvm.org/viewvc/llvm-project?rev=118126&view=rev
Log:
Make sure we're only storing a single bit here.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=118126&r1=118125&r2=118126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Nov  2 18:59:09 2010
@@ -811,7 +811,15 @@
   bool needReg0Op = false;
   switch (VT.getSimpleVT().SimpleTy) {
     default: return false;
-    case MVT::i1:
+    case MVT::i1: {
+      unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
+                                               ARM::GPRRegisterClass);
+      unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
+      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                              TII.get(Opc), Res)
+                      .addReg(SrcReg).addImm(1));
+      SrcReg = Res;
+    } // Fallthrough here.
     case MVT::i8:
       StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
       break;
@@ -841,7 +849,6 @@
   if (isFloat)
     Offset /= 4;
 
-
   // FIXME: The 'needReg0Op' bit goes away once STRH is converted to
   // not use the mega-addrmode stuff.
   if (!needReg0Op)