[llvm-commits] [llvm] r117857 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/X86/X86InstrInfo.td

[Chris Lattner]

Author: lattner
Date: Sun Oct 31 13:43:46 2010
New Revision: 117857

URL: http://llvm.org/viewvc/llvm-project?rev=117857&view=rev
Log:
sketch out the planned instruction alias mechanism, add some comments about
how the push/pop mnemonic aliases are wrong.

Modified:
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.td

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=117857&r1=117856&r2=117857&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Sun Oct 31 13:43:46 2010
@@ -567,6 +567,18 @@
   list<Predicate> Predicates = [];
 }
 
+/// InstAlias - This defines an alternate assembly syntax that is allowed to
+/// match an instruction that has a different (more canonical) assembly
+/// representation.
+class InstAlias<dag Outs, dag Ins, string Asm, dag Result> {
+  dag OutOperandList = Outs;   // An dag containing the MI def operand list.
+  dag InOperandList = Ins;     // An dag containing the MI use operand list.
+  string AsmString = Asm;      // The .s format to match the instruction with.
+  dag ResultInst = Result;     // The MCInst to generate.
+  
+  // Predicates - Predicates that must be true for this to match.
+  list<Predicate> Predicates = [];
+}
 
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=117857&r1=117856&r2=117857&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Oct 31 13:43:46 2010
@@ -1258,6 +1258,17 @@
 // Assembler Aliases
 //===----------------------------------------------------------------------===//
 
+// movsx aliases
+def : InstAlias<(outs GR32:$dst), (ins GR8 :$src),
+                "movsx $src, $dst",
+                (MOVSX32rr8 GR32:$dst, GR8:$src)>;
+def : InstAlias<(outs GR32:$dst), (ins GR16:$src),
+                "movsx $src, $dst",
+                (MOVSX32rr16 GR32:$dst, GR16:$src)>;
+
+
+// TODO: lidtl/lidtq can be opcode aliases, perhaps others.
+
 def : MnemonicAlias<"iret", "iretl">;
 def : MnemonicAlias<"sysret", "sysretl">;
 def : MnemonicAlias<"cbw",  "cbtw">;
@@ -1272,6 +1283,9 @@
 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"popfd",  "popfl">;
 
+// FIXME: This is wrong for "push reg".  "push %bx" should turn into pushw in
+// all modes.  However: "push (addr)" and "push $42" should default to
+// pushl/pushq depending on the current mode.  Similar for "pop %bx"
 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>;
 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>;
 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;