[llvm-commits] [llvm] r117720 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/vmla.ll

[Bob Wilson]

Author: bwilson
Date: Fri Oct 29 17:03:02 2010
New Revision: 117720

URL: http://llvm.org/viewvc/llvm-project?rev=117720&view=rev
Log:
Remove DAG combiner patch to fold vector splats.  Instcombiner does it now.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/ARM/vmla.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=117720&r1=117719&r2=117720&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Oct 29 17:03:02 2010
@@ -6362,11 +6362,6 @@
         V = ConvInput.getNode();
     }
 
-    // Fold a splat of a splat.
-    ShuffleVectorSDNode *SVV = dyn_cast<ShuffleVectorSDNode>(V);
-    if (SVV && SVV->isSplat())
-      return N0;
-
     if (V->getOpcode() == ISD::BUILD_VECTOR) {
       assert(V->getNumOperands() == NumElts &&
              "BUILD_VECTOR has wrong number of operands");

Modified: llvm/trunk/test/CodeGen/ARM/vmla.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmla.ll?rev=117720&r1=117719&r2=117720&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmla.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmla.ll Fri Oct 29 17:03:02 2010
@@ -213,19 +213,3 @@
   %4 = add <2 x i64> %arg0_uint64x2_t, %3
   ret <2 x i64> %4
 }
-
-; Redundant vector splats should be removed.  Radar 8597790.
-define void @fold_splat(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) nounwind {
-; CHECK: fold_splat
-; CHECK-NOT: vdup
-; CHECK: vmla.i32
-  %tmp1 = load <4 x i32>* %a, align 16
-  %tmp3 = load <4 x i32>* %b, align 16
-  %tmp5 = load <4 x i32>* %c, align 16
-  %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
-  %tmp7 = shufflevector <4 x i32> %tmp6, <4 x i32> undef, <4 x i32> zeroinitializer
-  %tmp8 = mul <4 x i32> %tmp3, %tmp7
-  %tmp9 = add <4 x i32> %tmp1, %tmp8
-  store <4 x i32> %tmp9, <4 x i32>* %a, align 16
-  ret void
-}