[llvm-commits] [llvm] r117396 - /llvm/trunk/test/MC/ARM/neon-shift-encoding.ll

[Owen Anderson]

Author: resistor
Date: Tue Oct 26 16:08:42 2010
New Revision: 117396

URL: http://llvm.org/viewvc/llvm-project?rev=117396&view=rev
Log:
Tests for NEON encoding of vshr.

Modified:
    llvm/trunk/test/MC/ARM/neon-shift-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.ll?rev=117396&r1=117395&r2=117396&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.ll Tue Oct 26 16:08:42 2010
@@ -134,3 +134,131 @@
 	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
 	ret <2 x i64> %tmp2
 }
+
+; CHECK: vshru_8xi8
+define <8 x i8> @vshru_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshr.u8	d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf3]
+	%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshru_4xi16
+define <4 x i16> @vshru_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshr.u16	d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf3]
+	%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshru_2xi32
+define <2 x i32> @vshru_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshr.u32	d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf3]
+	%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vshru_1xi64
+define <1 x i64> @vshru_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vshr.u64	d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf3]
+	%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vshru_16xi8
+define <16 x i8> @vshru_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vshr.u8	q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf3]
+	%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vshru_8xi16
+define <8 x i16> @vshru_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshr.u16	q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf3]
+	%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshru_4xi32
+define <4 x i32> @vshru_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshr.u32	q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf3]
+	%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshru_2xi64
+define <2 x i64> @vshru_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshr.u64	q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf3]
+	%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
+	ret <2 x i64> %tmp2
+}
+
+; CHECK: vshrs_8xi8
+define <8 x i8> @vshrs_8xi8(<8 x i8>* %A) nounwind {
+	%tmp1 = load <8 x i8>* %A
+; CHECK: vshr.s8	d16, d16, #8            @ encoding: [0x30,0x00,0xc8,0xf2
+	%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <8 x i8> %tmp2
+}
+
+; CHECK: vshrs_4xi16
+define <4 x i16> @vshrs_4xi16(<4 x i16>* %A) nounwind {
+	%tmp1 = load <4 x i16>* %A
+; CHECK: vshr.s16	d16, d16, #16   @ encoding: [0x30,0x00,0xd0,0xf2]
+	%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
+	ret <4 x i16> %tmp2
+}
+
+; CHECK: vshrs_2xi32
+define <2 x i32> @vshrs_2xi32(<2 x i32>* %A) nounwind {
+	%tmp1 = load <2 x i32>* %A
+; CHECK: vshr.s32	d16, d16, #32   @ encoding: [0x30,0x00,0xe0,0xf2]
+	%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
+	ret <2 x i32> %tmp2
+}
+
+; CHECK: vshrs_1xi64
+define <1 x i64> @vshrs_1xi64(<1 x i64>* %A) nounwind {
+	%tmp1 = load <1 x i64>* %A
+; CHECK: vshr.s64	d16, d16, #64   @ encoding: [0xb0,0x00,0xc0,0xf2]
+	%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
+	ret <1 x i64> %tmp2
+}
+
+; CHECK: vshrs_16xi8
+define <16 x i8> @vshrs_16xi8(<16 x i8>* %A) nounwind {
+	%tmp1 = load <16 x i8>* %A
+; CHECK: vshr.s8	q8, q8, #8              @ encoding: [0x70,0x00,0xc8,0xf2]
+	%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+	ret <16 x i8> %tmp2
+}
+
+; CHECK: vshrs_8xi16
+define <8 x i16> @vshrs_8xi16(<8 x i16>* %A) nounwind {
+	%tmp1 = load <8 x i16>* %A
+; CHECK: vshr.s16	q8, q8, #16     @ encoding: [0x70,0x00,0xd0,0xf2]
+	%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+	ret <8 x i16> %tmp2
+}
+
+; CHECK: vshrs_4xi32
+define <4 x i32> @vshrs_4xi32(<4 x i32>* %A) nounwind {
+	%tmp1 = load <4 x i32>* %A
+; CHECK: vshr.s32	q8, q8, #32     @ encoding: [0x70,0x00,0xe0,0xf2]
+	%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
+	ret <4 x i32> %tmp2
+}
+
+; CHECK: vshrs_2xi64
+define <2 x i64> @vshrs_2xi64(<2 x i64>* %A) nounwind {
+	%tmp1 = load <2 x i64>* %A
+; CHECK: vshr.s64	q8, q8, #64     @ encoding: [0xf0,0x00,0xc0,0xf2]
+	%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
+	ret <2 x i64> %tmp2
+}