[llvm-commits] [llvm] r117171 - /llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll

[Owen Anderson]

Author: resistor
Date: Fri Oct 22 18:02:27 2010
New Revision: 117171

URL: http://llvm.org/viewvc/llvm-project?rev=117171&view=rev
Log:
Add tests for NEON encoding of vmlsl.

Modified:
    llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll

Modified: llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll?rev=117171&r1=117170&r2=117171&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-mul-accum-encoding.ll Fri Oct 22 18:02:27 2010
@@ -276,3 +276,81 @@
 	%tmp5 = fsub <4 x float> %tmp1, %tmp4
 	ret <4 x float> %tmp5
 }
+
+; CHECK: vmlsls_8xi8
+define <8 x i16> @vmlsls_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+	%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
+; CHECK: vmlsl.s8	q8, d19, d18    @ encoding: [0xa2,0x0a,0xc3,0xf2]
+	%tmp6 = mul <8 x i16> %tmp4, %tmp5
+	%tmp7 = sub <8 x i16> %tmp1, %tmp6
+	ret <8 x i16> %tmp7
+}
+
+; CHECK: vmlsls_4xi16
+define <4 x i32> @vmlsls_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+	%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
+; CHECK: vmlsl.s16	q8, d19, d18    @ encoding: [0xa2,0x0a,0xd3,0xf2]
+	%tmp6 = mul <4 x i32> %tmp4, %tmp5
+	%tmp7 = sub <4 x i32> %tmp1, %tmp6
+	ret <4 x i32> %tmp7
+}
+
+; CHECK: vmlsls_2xi32
+define <2 x i64> @vmlsls_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+	%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
+; CHECK: vmlsl.s32	q8, d19, d18    @ encoding: [0xa2,0x0a,0xe3,0xf2]
+	%tmp6 = mul <2 x i64> %tmp4, %tmp5
+	%tmp7 = sub <2 x i64> %tmp1, %tmp6
+	ret <2 x i64> %tmp7
+}
+
+; CHECK: vmlslu_8xi8
+define <8 x i16> @vmlslu_8xi8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+	%tmp1 = load <8 x i16>* %A
+	%tmp2 = load <8 x i8>* %B
+	%tmp3 = load <8 x i8>* %C
+	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+	%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
+; CHECK: vmlsl.u8	q8, d19, d18    @ encoding: [0xa2,0x0a,0xc3,0xf3]
+	%tmp6 = mul <8 x i16> %tmp4, %tmp5
+	%tmp7 = sub <8 x i16> %tmp1, %tmp6
+	ret <8 x i16> %tmp7
+}
+
+; CHECK: vmlslu_4xi16
+define <4 x i32> @vmlslu_4xi16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+	%tmp1 = load <4 x i32>* %A
+	%tmp2 = load <4 x i16>* %B
+	%tmp3 = load <4 x i16>* %C
+	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+; CHECK: vmlsl.u16	q8, d19, d18    @ encoding: [0xa2,0x0a,0xd3,0xf3]
+	%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
+	%tmp6 = mul <4 x i32> %tmp4, %tmp5
+	%tmp7 = sub <4 x i32> %tmp1, %tmp6
+	ret <4 x i32> %tmp7
+}
+
+; CHECK: vmlslu_2xi32
+define <2 x i64> @vmlslu_2xi32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+	%tmp1 = load <2 x i64>* %A
+	%tmp2 = load <2 x i32>* %B
+	%tmp3 = load <2 x i32>* %C
+	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+	%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
+; CHECK: vmlsl.u32	q8, d19, d18    @ encoding: [0xa2,0x0a,0xe3,0xf3]
+	%tmp6 = mul <2 x i64> %tmp4, %tmp5
+	%tmp7 = sub <2 x i64> %tmp1, %tmp6
+	ret <2 x i64> %tmp7
+}