[llvm-commits] [llvm] r117076 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/simple-encoding.ll

[Jim Grosbach]

Author: grosbach
Date: Thu Oct 21 17:19:32 2010
New Revision: 117076

URL: http://llvm.org/viewvc/llvm-project?rev=117076&view=rev
Log:
ARM binary encodings for MVN variants.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/simple-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117076&r1=117075&r2=117076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Oct 21 17:19:32 2010
@@ -2207,22 +2207,39 @@
   let Inst{3-0}   = Rn;
 }
 
-def  MVNr  : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMVNr,
-                  "mvn", "\t$dst, $src",
-                  [(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
+def  MVNr  : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
+                  "mvn", "\t$Rd, $Rm",
+                  [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
+  bits<4> Rd;
+  bits<4> Rm;
   let Inst{25} = 0;
+  let Inst{19-16} = 0b0000;
   let Inst{11-4} = 0b00000000;
+  let Inst{15-12} = Rd;
+  let Inst{3-0} = Rm;
 }
-def  MVNs  : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
-                  IIC_iMVNsr, "mvn", "\t$dst, $src",
-                  [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
+def  MVNs  : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
+                  IIC_iMVNsr, "mvn", "\t$Rd, $shift",
+                  [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
+  bits<4> Rd;
+  bits<4> Rm;
+  bits<12> shift;
   let Inst{25} = 0;
+  let Inst{19-16} = 0b0000;
+  let Inst{15-12} = Rd;
+  let Inst{11-0} = shift;
 }
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def  MVNi  : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
-                  IIC_iMVNi, "mvn", "\t$dst, $imm",
-                  [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
-    let Inst{25} = 1;
+def  MVNi  : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
+                  IIC_iMVNi, "mvn", "\t$Rd, $imm",
+                  [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
+  bits<4> Rd;
+  bits<4> Rm;
+  bits<12> imm;
+  let Inst{25} = 1;
+  let Inst{19-16} = 0b0000;
+  let Inst{15-12} = Rd;
+  let Inst{11-0} = imm;
 }
 
 def : ARMPat<(and   GPR:$src, so_imm_not:$imm),

Modified: llvm/trunk/test/MC/ARM/simple-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-encoding.ll?rev=117076&r1=117075&r2=117076&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-encoding.ll Thu Oct 21 17:19:32 2010
@@ -99,7 +99,7 @@
   ret i64 %shr
 }
 
-define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) nounwind readnone ssp {
+define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) {
 entry:
 ; CHECK: f11
 ; CHECK: ubfx  r1, r1, #8, #5         @ encoding: [0x51,0x14,0xe4,0xe7]
@@ -121,4 +121,11 @@
     ret i32 %tmp
 }
 
+define i64 @f13() {
+; CHECK: f13:
+; CHECK: mvn r0, #0                   @ encoding: [0x00,0x00,0xe0,0xe3]
+; CHECK: mvn r1, #2, 2                @ encoding: [0x02,0x11,0xe0,0xe3]
+entry:
+        ret i64 9223372036854775807
+}
 declare void @llvm.trap() nounwind