[llvm-commits] [dragonegg] r115766 - /dragonegg/trunk/llvm-convert.cpp

[Duncan Sands]

Author: baldrick
Date: Wed Oct  6 02:26:04 2010
New Revision: 115766

URL: http://llvm.org/viewvc/llvm-project?rev=115766&view=rev
Log:
Port commit 104804 (bwilson) from llvm-gcc:
Avoid introducing an extra '=' in the constraint for an output register.
Fix a comment typo, too.


Modified:
    dragonegg/trunk/llvm-convert.cpp

Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=115766&r1=115765&r2=115766&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Wed Oct  6 02:26:04 2010
@@ -6852,12 +6852,11 @@
       if (RegNum >= 0) {
         RegName = LLVM_GET_REG_NAME(RegName, RegNum);
         unsigned RegNameLen = strlen(RegName);
-        char *NewConstraint = (char*)alloca(RegNameLen+4);
-        NewConstraint[0] = '=';
-        NewConstraint[1] = '{';
-        memcpy(NewConstraint+2, RegName, RegNameLen);
-        NewConstraint[RegNameLen+2] = '}';
-        NewConstraint[RegNameLen+3] = 0;
+        char *NewConstraint = (char*)alloca(RegNameLen+3);
+        NewConstraint[0] = '{';
+        memcpy(NewConstraint+1, RegName, RegNameLen);
+        NewConstraint[RegNameLen+1] = '}';
+        NewConstraint[RegNameLen+2] = 0;
         SimplifiedConstraint = NewConstraint;
         // This output will now be implicit; set the sideffect flag on the asm.
         HasSideEffects = true;