[llvm-commits] [llvm] r115744 - /llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
Chris Lattner
sabre at nondot.org
Tue Oct 5 21:58:43 PDT 2010
Author: lattner
Date: Tue Oct 5 23:58:43 2010
New Revision: 115744
URL: http://llvm.org/viewvc/llvm-project?rev=115744&view=rev
Log:
with tblgen suitably extended, we can now get the load node from typeinfo.
Modified:
llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=115744&r1=115743&r2=115744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Tue Oct 5 23:58:43 2010
@@ -538,14 +538,14 @@
class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
- SDNode opnode, PatFrag loadnode>
+ SDNode opnode>
: I<opcode, MRMSrcMem,
(outs typeinfo.RegClass:$dst),
(ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
!strconcat(mnemonic, "{", typeinfo.InstrSuffix,
"}\t{$src2, $dst|$dst, $src2}"),
[(set typeinfo.RegClass:$dst, EFLAGS,
- (opnode typeinfo.RegClass:$src1, (loadnode addr:$src2)))]>;
+ (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
// Logical operators.
@@ -576,10 +576,10 @@
"and{q}\t{$src2, $dst|$dst, $src2}", []>;
}
-def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag, loadi8 >;
-def AND16rm : BinOpRM<0x23, "and", Xi16, X86and_flag, loadi16>, OpSize;
-def AND32rm : BinOpRM<0x23, "and", Xi32, X86and_flag, loadi32>;
-def AND64rm : BinOpRM<0x23, "and", Xi64, X86and_flag, loadi64>, REX_W;
+def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag>;
+def AND16rm : BinOpRM<0x23, "and", Xi16, X86and_flag>, OpSize;
+def AND32rm : BinOpRM<0x23, "and", Xi32, X86and_flag>;
+def AND64rm : BinOpRM<0x23, "and", Xi64, X86and_flag>, REX_W;
def AND8ri : Ii8<0x80, MRM4r,
(outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
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