[llvm-commits] [llvm] r114768 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb2.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td ARMScheduleV6.td
Evan Cheng
evan.cheng at apple.com
Fri Sep 24 15:41:41 PDT 2010
Author: evancheng
Date: Fri Sep 24 17:41:41 2010
New Revision: 114768
URL: http://llvm.org/viewvc/llvm-project?rev=114768&view=rev
Log:
More pseudo instruction scheduling itinerary fixes.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/ARMSchedule.td
llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Sep 24 17:41:41 2010
@@ -2711,7 +2711,7 @@
// scheduling.
let canFoldAsLoad = 1, isReMaterializable = 1 in
def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
- NoItinerary,
+ IIC_iLoadiALU,
"${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
[(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
imm:$cp))]>,
Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Sep 24 17:41:41 2010
@@ -45,6 +45,7 @@
def IIC_iLoadsiu : InstrItinClass;
def IIC_iLoadm : InstrItinClass<0>; // micro-coded
def IIC_iLoadmBr : InstrItinClass<0>; // micro-coded
+def IIC_iLoadiALU : InstrItinClass;
def IIC_iStorei : InstrItinClass;
def IIC_iStorer : InstrItinClass;
def IIC_iStoresi : InstrItinClass;
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Sep 24 17:41:41 2010
@@ -51,7 +51,7 @@
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
- InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
+ InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,
@@ -133,6 +133,14 @@
InstrStage<1, [A8_LdSt0]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>,
+ //
+ // iLoadi + iALUr for t2LDRpci_pic.
+ InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Issue], 0>,
+ InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrStage<1, [A8_LdSt0]>,
+ InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>,
+
+
// Integer store pipeline
//
// use A8_Issue to enforce the 1 load/store per cycle limit
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Sep 24 17:41:41 2010
@@ -33,7 +33,7 @@
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
- InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
+ InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
@@ -115,6 +115,12 @@
InstrStage<1, [A9_LSPipe]>,
InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
+ //
+ // iLoadi + iALUr for t2LDRpci_pic.
+ InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
+ InstrStage<1, [A9_LSPipe]>,
+ InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
+
// Integer store pipeline
///
// Immediate offset
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=114768&r1=114767&r2=114768&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Fri Sep 24 17:41:41 2010
@@ -46,6 +46,8 @@
InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>,
+ InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>,
+ InstrStage<1, [V6_Pipe]>], [2]>,
//
// Move instructions, conditional
InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>,
@@ -91,6 +93,11 @@
InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>,
InstrStage<1, [V6_Pipe]>]>,
+ //
+ // iLoadi + iALUr for t2LDRpci_pic.
+ InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
+ InstrStage<1, [V6_Pipe]>], [3, 1]>,
+
// Integer store pipeline
//
// Immediate offset
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