[llvm-commits] [llvm] r114696 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/vld1.ll test/CodeGen/ARM/vld2.ll test/CodeGen/ARM/vld3.ll test/CodeGen/ARM/vld4.ll
Bob Wilson
bob.wilson at apple.com
Thu Sep 23 14:43:54 PDT 2010
Author: bwilson
Date: Thu Sep 23 16:43:54 2010
New Revision: 114696
URL: http://llvm.org/viewvc/llvm-project?rev=114696&view=rev
Log:
Set alignment operand for NEON VLD instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/ARM/vld1.ll
llvm/trunk/test/CodeGen/ARM/vld2.ll
llvm/trunk/test/CodeGen/ARM/vld3.ll
llvm/trunk/test/CodeGen/ARM/vld4.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Sep 23 16:43:54 2010
@@ -1016,6 +1016,22 @@
EVT VT = N->getValueType(0);
bool is64BitVector = VT.is64BitVector();
+ // Set the alignment. The supported values depend on the number of
+ // registers being loaded.
+ unsigned NumRegs = NumVecs;
+ if (!is64BitVector && NumVecs < 3)
+ NumRegs *= 2;
+ unsigned Alignment = cast<MemIntrinsicSDNode>(N)->getAlignment();
+ if (Alignment >= 32 && NumRegs == 4)
+ Alignment = 32;
+ else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
+ Alignment = 16;
+ else if (Alignment >= 8)
+ Alignment = 8;
+ else
+ Alignment = 0;
+ Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
+
unsigned OpcodeIndex;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld type");
Modified: llvm/trunk/test/CodeGen/ARM/vld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld1.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld1.ll Thu Sep 23 16:43:54 2010
@@ -2,8 +2,9 @@
define <8 x i8> @vld1i8(i8* %A) nounwind {
;CHECK: vld1i8:
-;CHECK: vld1.8
- %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 64 bits:
+;CHECK: vld1.8 {d0}, [r0, :64]
+ %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
ret <8 x i8> %tmp1
}
@@ -41,8 +42,9 @@
define <16 x i8> @vld1Qi8(i8* %A) nounwind {
;CHECK: vld1Qi8:
-;CHECK: vld1.8
- %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 128 bits:
+;CHECK: vld1.8 {d0, d1}, [r0, :128]
+ %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 32)
ret <16 x i8> %tmp1
}
Modified: llvm/trunk/test/CodeGen/ARM/vld2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld2.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld2.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
define <8 x i8> @vld2i8(i8* %A) nounwind {
;CHECK: vld2i8:
-;CHECK: vld2.8
- %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 128 bits:
+;CHECK: vld2.8 {d0, d1}, [r0, :64]
+ %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
%tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -23,9 +24,10 @@
define <4 x i16> @vld2i16(i16* %A) nounwind {
;CHECK: vld2i16:
-;CHECK: vld2.16
+;Check the alignment value. Max for this instruction is 128 bits:
+;CHECK: vld2.16 {d0, d1}, [r0, :128]
%tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
%tmp4 = add <4 x i16> %tmp2, %tmp3
@@ -56,9 +58,10 @@
define <1 x i64> @vld2i64(i64* %A) nounwind {
;CHECK: vld2i64:
-;CHECK: vld1.64
+;Check the alignment value. Max for this instruction is 128 bits:
+;CHECK: vld1.64 {d0, d1}, [r0, :128]
%tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
%tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,8 +70,9 @@
define <16 x i8> @vld2Qi8(i8* %A) nounwind {
;CHECK: vld2Qi8:
-;CHECK: vld2.8
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld2.8 {d0, d1, d2, d3}, [r0, :64]
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
%tmp4 = add <16 x i8> %tmp2, %tmp3
@@ -77,9 +81,10 @@
define <8 x i16> @vld2Qi16(i16* %A) nounwind {
;CHECK: vld2Qi16:
-;CHECK: vld2.16
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld2.16 {d0, d1, d2, d3}, [r0, :128]
%tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
%tmp4 = add <8 x i16> %tmp2, %tmp3
@@ -88,9 +93,10 @@
define <4 x i32> @vld2Qi32(i32* %A) nounwind {
;CHECK: vld2Qi32:
-;CHECK: vld2.32
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld2.32 {d0, d1, d2, d3}, [r0, :256]
%tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64)
%tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
%tmp4 = add <4 x i32> %tmp2, %tmp3
Modified: llvm/trunk/test/CodeGen/ARM/vld3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld3.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld3.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
define <8 x i8> @vld3i8(i8* %A) nounwind {
;CHECK: vld3i8:
-;CHECK: vld3.8
- %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 64 bits:
+;CHECK: vld3.8 {d0, d1, d2}, [r0, :64]
+ %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
%tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -56,9 +57,10 @@
define <1 x i64> @vld3i64(i64* %A) nounwind {
;CHECK: vld3i64:
-;CHECK: vld1.64
+;Check the alignment value. Max for this instruction is 64 bits:
+;CHECK: vld1.64 {d0, d1, d2}, [r0, :64]
%tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,9 +69,10 @@
define <16 x i8> @vld3Qi8(i8* %A) nounwind {
;CHECK: vld3Qi8:
-;CHECK: vld3.8
-;CHECK: vld3.8
- %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 64 bits:
+;CHECK: vld3.8 {d0, d2, d4}, [r0, :64]!
+;CHECK: vld3.8 {d1, d3, d5}, [r0, :64]
+ %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
%tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
%tmp4 = add <16 x i8> %tmp2, %tmp3
Modified: llvm/trunk/test/CodeGen/ARM/vld4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vld4.ll?rev=114696&r1=114695&r2=114696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vld4.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vld4.ll Thu Sep 23 16:43:54 2010
@@ -13,8 +13,9 @@
define <8 x i8> @vld4i8(i8* %A) nounwind {
;CHECK: vld4i8:
-;CHECK: vld4.8
- %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld4.8 {d0, d1, d2, d3}, [r0, :64]
+ %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
%tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
%tmp4 = add <8 x i8> %tmp2, %tmp3
@@ -23,9 +24,10 @@
define <4 x i16> @vld4i16(i16* %A) nounwind {
;CHECK: vld4i16:
-;CHECK: vld4.16
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld4.16 {d0, d1, d2, d3}, [r0, :128]
%tmp0 = bitcast i16* %A to i8*
- %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
%tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2
%tmp4 = add <4 x i16> %tmp2, %tmp3
@@ -34,9 +36,10 @@
define <2 x i32> @vld4i32(i32* %A) nounwind {
;CHECK: vld4i32:
-;CHECK: vld4.32
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld4.32 {d0, d1, d2, d3}, [r0, :256]
%tmp0 = bitcast i32* %A to i8*
- %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
%tmp4 = add <2 x i32> %tmp2, %tmp3
@@ -56,9 +59,10 @@
define <1 x i64> @vld4i64(i64* %A) nounwind {
;CHECK: vld4i64:
-;CHECK: vld1.64
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld1.64 {d0, d1, d2, d3}, [r0, :256]
%tmp0 = bitcast i64* %A to i8*
- %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 1)
+ %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
%tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2
%tmp4 = add <1 x i64> %tmp2, %tmp3
@@ -67,9 +71,10 @@
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
;CHECK: vld4Qi8:
-;CHECK: vld4.8
-;CHECK: vld4.8
- %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 1)
+;Check the alignment value. Max for this instruction is 256 bits:
+;CHECK: vld4.8 {d0, d2, d4, d6}, [r0, :256]!
+;CHECK: vld4.8 {d1, d3, d5, d7}, [r0, :256]
+ %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
%tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
%tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
%tmp4 = add <16 x i8> %tmp2, %tmp3
@@ -78,8 +83,9 @@
define <8 x i16> @vld4Qi16(i16* %A) nounwind {
;CHECK: vld4Qi16:
-;CHECK: vld4.16
-;CHECK: vld4.16
+;Check for no alignment specifier.
+;CHECK: vld4.16 {d0, d2, d4, d6}, [r0]!
+;CHECK: vld4.16 {d1, d3, d5, d7}, [r0]
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 1)
%tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0
More information about the llvm-commits
mailing list