[llvm-commits] [llvm] r113983 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll

[Bob Wilson]

Author: bwilson
Date: Wed Sep 15 12:12:08 2010
New Revision: 113983

URL: http://llvm.org/viewvc/llvm-project?rev=113983&view=rev
Log:
Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113983&r1=113982&r2=113983&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 12:12:08 2010
@@ -1352,6 +1352,21 @@
     SrcReg = MI->getOperand(0).getReg();
     CmpValue = MI->getOperand(1).getImm();
     return true;
+  case ARM::TSTri: {
+    MachineBasicBlock::const_iterator MII(MI);
+    if (MI->getParent()->begin() == MII)
+      return false;
+    const MachineInstr *AND = llvm::prior(MII);
+    if (AND->getOpcode() != ARM::ANDri)
+      return false;
+    if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
+        MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
+      SrcReg = AND->getOperand(0).getReg();
+      CmpValue = 0;
+      return true;
+    }
+    }
+    break;
   }
 
   return false;
@@ -1401,6 +1416,8 @@
   switch (MI->getOpcode()) {
   default: break;
   case ARM::ADDri:
+  case ARM::ANDri:
+  case ARM::t2ANDri:
   case ARM::SUBri:
   case ARM::t2ADDri:
   case ARM::t2SUBri:

Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113983&r1=113982&r2=113983&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Wed Sep 15 12:12:08 2010
@@ -17,8 +17,7 @@
   %tmp2 = load i8** %scevgep5
   %0 = ptrtoint i8* %tmp2 to i32
 
-; CHECK:      and lr, r12, #3
-; CHECK-NEXT: tst r12, #3
+; CHECK:      ands r12, r12, #3
 ; CHECK-NEXT: beq LBB0_4
 
 ; T2:      movs r5, #3